kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/x86/events/intel/uncore.h
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@@ -2,6 +2,7 @@
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 #include <linux/slab.h>
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 #include <linux/pci.h>
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 #include <asm/apicdef.h>
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+#include <linux/io-64-nonatomic-lo-hi.h>
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 #include <linux/perf_event.h>
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 #include "../perf_event.h"
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@@ -56,7 +57,11 @@
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 	unsigned fixed_ctr;
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 	unsigned fixed_ctl;
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 	unsigned box_ctl;
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-	unsigned msr_offset;
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+	union {
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+		unsigned msr_offset;
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+		unsigned mmio_offset;
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+	};
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+	unsigned mmio_map_size;
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 	unsigned num_shared_regs:8;
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 	unsigned single_fixed:1;
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 	unsigned pair_ctr_ctl:1;
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@@ -68,7 +73,19 @@
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 	struct uncore_event_desc *event_descs;
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 	struct freerunning_counters *freerunning;
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 	const struct attribute_group *attr_groups[4];
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+	const struct attribute_group **attr_update;
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 	struct pmu *pmu; /* for custom pmu ops */
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+	/*
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+	 * Uncore PMU would store relevant platform topology configuration here
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+	 * to identify which platform component each PMON block of that type is
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+	 * supposed to monitor.
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+	 */
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+	u64 *topology;
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+	/*
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+	 * Optional callbacks for managing mapping of Uncore units to PMONs
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+	 */
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+	int (*set_mapping)(struct intel_uncore_type *type);
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+	void (*cleanup_mapping)(struct intel_uncore_type *type);
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 };
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 #define pmu_group attr_groups[0]
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@@ -108,7 +125,7 @@
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 struct intel_uncore_box {
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 	int pci_phys_id;
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-	int pkgid;	/* Logical package ID */
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+	int dieid;	/* Logical die ID */
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 	int n_active;	/* number of active events */
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 	int n_events;
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 	int cpu;	/* cpu to collect events */
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@@ -125,12 +142,19 @@
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 	struct hrtimer hrtimer;
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 	struct list_head list;
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 	struct list_head active_list;
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-	void *io_addr;
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-	struct intel_uncore_extra_reg shared_regs[0];
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+	void __iomem *io_addr;
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+	struct intel_uncore_extra_reg shared_regs[];
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 };
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-#define UNCORE_BOX_FLAG_INITIATED	0
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-#define UNCORE_BOX_FLAG_CTL_OFFS8	1 /* event config registers are 8-byte apart */
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+/* CFL uncore 8th cbox MSRs */
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+#define CFL_UNC_CBO_7_PERFEVTSEL0		0xf70
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+#define CFL_UNC_CBO_7_PER_CTR0			0xf76
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+
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+#define UNCORE_BOX_FLAG_INITIATED		0
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+/* event config registers are 8-byte apart */
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+#define UNCORE_BOX_FLAG_CTL_OFFS8		1
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+/* CFL 8th CBOX has different MSR space */
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+#define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS	2
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158
 
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 struct uncore_event_desc {
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 	struct device_attribute attr;
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@@ -143,6 +167,7 @@
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 	unsigned int box_offset;
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 	unsigned int num_counters;
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 	unsigned int bits;
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+	unsigned *box_offsets;
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 };
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 struct pci2phy_map {
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@@ -152,9 +177,22 @@
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 };
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 struct pci2phy_map *__find_pci2phy_map(int segment);
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+int uncore_pcibus_to_physid(struct pci_bus *bus);
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 ssize_t uncore_event_show(struct device *dev,
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 			  struct device_attribute *attr, char *buf);
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+
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+static inline struct intel_uncore_pmu *dev_to_uncore_pmu(struct device *dev)
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+{
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+	return container_of(dev_get_drvdata(dev), struct intel_uncore_pmu, pmu);
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+}
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+
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+#define to_device_attribute(n)	container_of(n, struct device_attribute, attr)
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+#define to_dev_ext_attribute(n)	container_of(n, struct dev_ext_attribute, attr)
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+#define attr_to_ext_attr(n)	to_dev_ext_attribute(to_device_attribute(n))
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+
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+extern int __uncore_max_dies;
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+#define uncore_max_dies()	(__uncore_max_dies)
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 #define INTEL_UNCORE_EVENT_DESC(_name, _config)			\
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 {								\
..
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@@ -181,6 +219,25 @@
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 static inline bool uncore_pmc_freerunning(int idx)
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 {
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 	return idx == UNCORE_PMC_IDX_FREERUNNING;
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+}
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+
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+static inline bool uncore_mmio_is_valid_offset(struct intel_uncore_box *box,
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+					       unsigned long offset)
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+{
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+	if (offset < box->pmu->type->mmio_map_size)
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+		return true;
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+
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+	pr_warn_once("perf uncore: Invalid offset 0x%lx exceeds mapped area of %s.\n",
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+		     offset, box->pmu->type->name);
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+
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+	return false;
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+}
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+
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+static inline
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+unsigned int uncore_mmio_box_ctl(struct intel_uncore_box *box)
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+{
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+	return box->pmu->type->box_ctl +
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+	       box->pmu->type->mmio_offset * box->pmu->pmu_idx;
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 }
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 static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
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@@ -291,29 +348,41 @@
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 	return pmu->type->freerunning[type].counter_base +
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 	       pmu->type->freerunning[type].counter_offset * idx +
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-	       pmu->type->freerunning[type].box_offset * pmu->pmu_idx;
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+	       (pmu->type->freerunning[type].box_offsets ?
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+	        pmu->type->freerunning[type].box_offsets[pmu->pmu_idx] :
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+	        pmu->type->freerunning[type].box_offset * pmu->pmu_idx);
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 }
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 static inline
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 unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
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 {
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-	return box->pmu->type->event_ctl +
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-		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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-		uncore_msr_box_offset(box);
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+	if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
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+		return CFL_UNC_CBO_7_PERFEVTSEL0 +
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+		       (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
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+	} else {
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+		return box->pmu->type->event_ctl +
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+		       (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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+		       uncore_msr_box_offset(box);
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+	}
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 }
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 static inline
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 unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
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 {
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-	return box->pmu->type->perf_ctr +
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-		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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-		uncore_msr_box_offset(box);
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+	if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
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+		return CFL_UNC_CBO_7_PER_CTR0 +
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+		       (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
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+	} else {
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+		return box->pmu->type->perf_ctr +
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+		       (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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+		       uncore_msr_box_offset(box);
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+	}
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 }
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 static inline
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 unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
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 {
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-	if (box->pci_dev)
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+	if (box->pci_dev || box->io_addr)
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 		return uncore_pci_fixed_ctl(box);
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 	else
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 		return uncore_msr_fixed_ctl(box);
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@@ -322,7 +391,7 @@
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 static inline
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 unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
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 {
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-	if (box->pci_dev)
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+	if (box->pci_dev || box->io_addr)
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 		return uncore_pci_fixed_ctr(box);
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 	else
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 		return uncore_msr_fixed_ctr(box);
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@@ -331,7 +400,7 @@
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 static inline
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 unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
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 {
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-	if (box->pci_dev)
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+	if (box->pci_dev || box->io_addr)
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 		return uncore_pci_event_ctl(box, idx);
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 	else
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 		return uncore_msr_event_ctl(box, idx);
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@@ -340,7 +409,7 @@
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 static inline
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 unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
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 {
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-	if (box->pci_dev)
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+	if (box->pci_dev || box->io_addr)
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 		return uncore_pci_perf_ctr(box, idx);
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 	else
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 		return uncore_msr_perf_ctr(box, idx);
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@@ -448,7 +517,7 @@
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 static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
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 {
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-	return (box->pkgid < 0);
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+	return (box->dieid < 0);
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 }
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 static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
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@@ -463,6 +532,9 @@
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 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
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 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
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+void uncore_mmio_exit_box(struct intel_uncore_box *box);
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+u64 uncore_mmio_read_counter(struct intel_uncore_box *box,
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+			     struct perf_event *event);
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 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
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 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
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 void uncore_pmu_event_start(struct perf_event *event, int flags);
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@@ -478,7 +550,9 @@
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 extern struct intel_uncore_type **uncore_msr_uncores;
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 extern struct intel_uncore_type **uncore_pci_uncores;
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+extern struct intel_uncore_type **uncore_mmio_uncores;
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 extern struct pci_driver *uncore_pci_driver;
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+extern struct pci_driver *uncore_pci_sub_driver;
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 extern raw_spinlock_t pci2phy_map_lock;
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 extern struct list_head pci2phy_map_head;
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 extern struct pci_extra_dev *uncore_extra_pci_dev;
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@@ -493,6 +567,10 @@
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 void snb_uncore_cpu_init(void);
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 void nhm_uncore_cpu_init(void);
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 void skl_uncore_cpu_init(void);
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+void icl_uncore_cpu_init(void);
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+void tgl_uncore_cpu_init(void);
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+void tgl_uncore_mmio_init(void);
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+void tgl_l_uncore_mmio_init(void);
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 int snb_pci2phy_map_init(int devid);
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 /* uncore_snbep.c */
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@@ -508,6 +586,12 @@
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 void knl_uncore_cpu_init(void);
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 int skx_uncore_pci_init(void);
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 void skx_uncore_cpu_init(void);
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+int snr_uncore_pci_init(void);
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+void snr_uncore_cpu_init(void);
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+void snr_uncore_mmio_init(void);
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+int icx_uncore_pci_init(void);
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+void icx_uncore_cpu_init(void);
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+void icx_uncore_mmio_init(void);
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 /* uncore_nhmex.c */
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 void nhmex_uncore_cpu_init(void);