kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/riscv/kernel/perf_event.c
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@@ -147,7 +147,7 @@
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 	return riscv_pmu->hw_events[config];
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 }
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-int riscv_map_cache_decode(u64 config, unsigned int *type,
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+static int riscv_map_cache_decode(u64 config, unsigned int *type,
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 			   unsigned int *op, unsigned int *result)
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 {
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 	return -ENOENT;
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@@ -185,10 +185,10 @@
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 	switch (idx) {
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 	case RISCV_PMU_CYCLE:
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-		val = csr_read(cycle);
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+		val = csr_read(CSR_CYCLE);
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 		break;
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 	case RISCV_PMU_INSTRET:
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-		val = csr_read(instret);
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+		val = csr_read(CSR_INSTRET);
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 		break;
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 	default:
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 		WARN_ON_ONCE(idx < 0 ||	idx > RISCV_MAX_COUNTERS);
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@@ -342,7 +342,7 @@
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 static DEFINE_MUTEX(pmc_reserve_mutex);
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-irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev)
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+static irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev)
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 {
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 	return IRQ_NONE;
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 }
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@@ -361,7 +361,7 @@
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 	return err;
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 }
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-void release_pmc_hardware(void)
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+static void release_pmc_hardware(void)
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 {
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 	mutex_lock(&pmc_reserve_mutex);
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 	if (riscv_pmu->irq >= 0)
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@@ -464,7 +464,7 @@
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 	{ /* sentinel value */ }
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 };
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-int __init init_hw_perf_events(void)
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+static int __init init_hw_perf_events(void)
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 {
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 	struct device_node *node = of_find_node_by_type(NULL, "pmu");
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 	const struct of_device_id *of_id;
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@@ -476,6 +476,7 @@
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 		if (of_id)
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 			riscv_pmu = of_id->data;
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+		of_node_put(node);
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 	}
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 	perf_pmu_register(riscv_pmu->pmu, "cpu", PERF_TYPE_RAW);