kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/riscv/include/asm/perf_event.h
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@@ -12,19 +12,14 @@
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 #include <linux/ptrace.h>
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 #include <linux/interrupt.h>
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+#ifdef CONFIG_RISCV_BASE_PMU
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 #define RISCV_BASE_COUNTERS	2
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 /*
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  * The RISCV_MAX_COUNTERS parameter should be specified.
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  */
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-#ifdef CONFIG_RISCV_BASE_PMU
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 #define RISCV_MAX_COUNTERS	2
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-#endif
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-
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-#ifndef RISCV_MAX_COUNTERS
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-#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU."
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-#endif
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 /*
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  * These are the indexes of bits in counteren register *minus* 1,
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@@ -82,4 +77,9 @@
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 	int		irq;
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 };
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+#endif
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+#ifdef CONFIG_PERF_EVENTS
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+#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs
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+#endif
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+
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 #endif /* _ASM_RISCV_PERF_EVENT_H */