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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/arch/riscv/include/asm/io.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
34  *   which was based on arch/arm/include/io.h
....@@ -5,180 +6,29 @@
56  * Copyright (C) 1996-2000 Russell King
67  * Copyright (C) 2012 ARM Ltd.
78  * Copyright (C) 2014 Regents of the University of California
8
- *
9
- *   This program is free software; you can redistribute it and/or
10
- *   modify it under the terms of the GNU General Public License
11
- *   as published by the Free Software Foundation, version 2.
12
- *
13
- *   This program is distributed in the hope that it will be useful,
14
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
- *   GNU General Public License for more details.
179  */
1810 
1911 #ifndef _ASM_RISCV_IO_H
2012 #define _ASM_RISCV_IO_H
2113 
2214 #include <linux/types.h>
23
-
24
-extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
15
+#include <linux/pgtable.h>
16
+#include <asm/mmiowb.h>
17
+#include <asm/early_ioremap.h>
2518 
2619 /*
27
- * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
28
- * change the properties of memory regions.  This should be fixed by the
29
- * upcoming platform spec.
20
+ * MMIO access functions are separated out to break dependency cycles
21
+ * when using {read,write}* fns in low-level headers
3022  */
31
-#define ioremap_nocache(addr, size) ioremap((addr), (size))
32
-#define ioremap_wc(addr, size) ioremap((addr), (size))
33
-#define ioremap_wt(addr, size) ioremap((addr), (size))
34
-
35
-extern void iounmap(volatile void __iomem *addr);
36
-
37
-/* Generic IO read/write.  These perform native-endian accesses. */
38
-#define __raw_writeb __raw_writeb
39
-static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
40
-{
41
-	asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
42
-}
43
-
44
-#define __raw_writew __raw_writew
45
-static inline void __raw_writew(u16 val, volatile void __iomem *addr)
46
-{
47
-	asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
48
-}
49
-
50
-#define __raw_writel __raw_writel
51
-static inline void __raw_writel(u32 val, volatile void __iomem *addr)
52
-{
53
-	asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
54
-}
55
-
56
-#ifdef CONFIG_64BIT
57
-#define __raw_writeq __raw_writeq
58
-static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
59
-{
60
-	asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
61
-}
62
-#endif
63
-
64
-#define __raw_readb __raw_readb
65
-static inline u8 __raw_readb(const volatile void __iomem *addr)
66
-{
67
-	u8 val;
68
-
69
-	asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
70
-	return val;
71
-}
72
-
73
-#define __raw_readw __raw_readw
74
-static inline u16 __raw_readw(const volatile void __iomem *addr)
75
-{
76
-	u16 val;
77
-
78
-	asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
79
-	return val;
80
-}
81
-
82
-#define __raw_readl __raw_readl
83
-static inline u32 __raw_readl(const volatile void __iomem *addr)
84
-{
85
-	u32 val;
86
-
87
-	asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
88
-	return val;
89
-}
90
-
91
-#ifdef CONFIG_64BIT
92
-#define __raw_readq __raw_readq
93
-static inline u64 __raw_readq(const volatile void __iomem *addr)
94
-{
95
-	u64 val;
96
-
97
-	asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
98
-	return val;
99
-}
100
-#endif
23
+#include <asm/mmio.h>
10124 
10225 /*
103
- * FIXME: I'm flip-flopping on whether or not we should keep this or enforce
104
- * the ordering with I/O on spinlocks like PowerPC does.  The worry is that
105
- * drivers won't get this correct, but I also don't want to introduce a fence
106
- * into the lock code that otherwise only uses AMOs (and is essentially defined
107
- * by the ISA to be correct).   For now I'm leaving this here: "o,w" is
108
- * sufficient to ensure that all writes to the device have completed before the
109
- * write to the spinlock is allowed to commit.  I surmised this from reading
110
- * "ACQUIRES VS I/O ACCESSES" in memory-barriers.txt.
26
+ *  I/O port access constants.
11127  */
112
-#define mmiowb()	__asm__ __volatile__ ("fence o,w" : : : "memory");
113
-
114
-/*
115
- * Unordered I/O memory access primitives.  These are even more relaxed than
116
- * the relaxed versions, as they don't even order accesses between successive
117
- * operations to the I/O regions.
118
- */
119
-#define readb_cpu(c)		({ u8  __r = __raw_readb(c); __r; })
120
-#define readw_cpu(c)		({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
121
-#define readl_cpu(c)		({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
122
-
123
-#define writeb_cpu(v,c)		((void)__raw_writeb((v),(c)))
124
-#define writew_cpu(v,c)		((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
125
-#define writel_cpu(v,c)		((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
126
-
127
-#ifdef CONFIG_64BIT
128
-#define readq_cpu(c)		({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
129
-#define writeq_cpu(v,c)		((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
130
-#endif
131
-
132
-/*
133
- * Relaxed I/O memory access primitives. These follow the Device memory
134
- * ordering rules but do not guarantee any ordering relative to Normal memory
135
- * accesses.  These are defined to order the indicated access (either a read or
136
- * write) with all other I/O memory accesses. Since the platform specification
137
- * defines that all I/O regions are strongly ordered on channel 2, no explicit
138
- * fences are required to enforce this ordering.
139
- */
140
-/* FIXME: These are now the same as asm-generic */
141
-#define __io_rbr()		do {} while (0)
142
-#define __io_rar()		do {} while (0)
143
-#define __io_rbw()		do {} while (0)
144
-#define __io_raw()		do {} while (0)
145
-
146
-#define readb_relaxed(c)	({ u8  __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
147
-#define readw_relaxed(c)	({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
148
-#define readl_relaxed(c)	({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
149
-
150
-#define writeb_relaxed(v,c)	({ __io_rbw(); writeb_cpu((v),(c)); __io_raw(); })
151
-#define writew_relaxed(v,c)	({ __io_rbw(); writew_cpu((v),(c)); __io_raw(); })
152
-#define writel_relaxed(v,c)	({ __io_rbw(); writel_cpu((v),(c)); __io_raw(); })
153
-
154
-#ifdef CONFIG_64BIT
155
-#define readq_relaxed(c)	({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
156
-#define writeq_relaxed(v,c)	({ __io_rbw(); writeq_cpu((v),(c)); __io_raw(); })
157
-#endif
158
-
159
-/*
160
- * I/O memory access primitives. Reads are ordered relative to any
161
- * following Normal memory access. Writes are ordered relative to any prior
162
- * Normal memory access.  The memory barriers here are necessary as RISC-V
163
- * doesn't define any ordering between the memory space and the I/O space.
164
- */
165
-#define __io_br()	do {} while (0)
166
-#define __io_ar()	__asm__ __volatile__ ("fence i,r" : : : "memory");
167
-#define __io_bw()	__asm__ __volatile__ ("fence w,o" : : : "memory");
168
-#define __io_aw()	do {} while (0)
169
-
170
-#define readb(c)	({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(); __v; })
171
-#define readw(c)	({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(); __v; })
172
-#define readl(c)	({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(); __v; })
173
-
174
-#define writeb(v,c)	({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); })
175
-#define writew(v,c)	({ __io_bw(); writew_cpu((v),(c)); __io_aw(); })
176
-#define writel(v,c)	({ __io_bw(); writel_cpu((v),(c)); __io_aw(); })
177
-
178
-#ifdef CONFIG_64BIT
179
-#define readq(c)	({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(); __v; })
180
-#define writeq(v,c)	({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); })
181
-#endif
28
+#ifdef CONFIG_MMU
29
+#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
30
+#define PCI_IOBASE		((void __iomem *)PCI_IO_START)
31
+#endif /* CONFIG_MMU */
18232 
18333 /*
18434  * Emulation routines for the port-mapped IO space used by some PCI drivers.
....@@ -198,20 +48,20 @@
19848  * writes.
19949  */
20050 #define __io_pbr()	__asm__ __volatile__ ("fence io,i"  : : : "memory");
201
-#define __io_par()	__asm__ __volatile__ ("fence i,ior" : : : "memory");
51
+#define __io_par(v)	__asm__ __volatile__ ("fence i,ior" : : : "memory");
20252 #define __io_pbw()	__asm__ __volatile__ ("fence iow,o" : : : "memory");
20353 #define __io_paw()	__asm__ __volatile__ ("fence o,io"  : : : "memory");
20454 
205
-#define inb(c)		({ u8  __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
206
-#define inw(c)		({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
207
-#define inl(c)		({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
55
+#define inb(c)		({ u8  __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
56
+#define inw(c)		({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
57
+#define inl(c)		({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
20858 
20959 #define outb(v,c)	({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
21060 #define outw(v,c)	({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
21161 #define outl(v,c)	({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
21262 
21363 #ifdef CONFIG_64BIT
214
-#define inq(c)		({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(); __v; })
64
+#define inq(c)		({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
21565 #define outq(v,c)	({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
21666 #endif
21767 
....@@ -254,19 +104,19 @@
254104 		afence;								\
255105 	}
256106 
257
-__io_reads_ins(reads,  u8, b, __io_br(), __io_ar())
258
-__io_reads_ins(reads, u16, w, __io_br(), __io_ar())
259
-__io_reads_ins(reads, u32, l, __io_br(), __io_ar())
107
+__io_reads_ins(reads,  u8, b, __io_br(), __io_ar(addr))
108
+__io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
109
+__io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
260110 #define readsb(addr, buffer, count) __readsb(addr, buffer, count)
261111 #define readsw(addr, buffer, count) __readsw(addr, buffer, count)
262112 #define readsl(addr, buffer, count) __readsl(addr, buffer, count)
263113 
264
-__io_reads_ins(ins,  u8, b, __io_pbr(), __io_par())
265
-__io_reads_ins(ins, u16, w, __io_pbr(), __io_par())
266
-__io_reads_ins(ins, u32, l, __io_pbr(), __io_par())
267
-#define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
268
-#define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
269
-#define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
114
+__io_reads_ins(ins,  u8, b, __io_pbr(), __io_par(addr))
115
+__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
116
+__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
117
+#define insb(addr, buffer, count) __insb(PCI_IOBASE + (addr), buffer, count)
118
+#define insw(addr, buffer, count) __insw(PCI_IOBASE + (addr), buffer, count)
119
+#define insl(addr, buffer, count) __insl(PCI_IOBASE + (addr), buffer, count)
270120 
271121 __io_writes_outs(writes,  u8, b, __io_bw(), __io_aw())
272122 __io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
....@@ -278,22 +128,22 @@
278128 __io_writes_outs(outs,  u8, b, __io_pbw(), __io_paw())
279129 __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
280130 __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
281
-#define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
282
-#define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
283
-#define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
131
+#define outsb(addr, buffer, count) __outsb(PCI_IOBASE + (addr), buffer, count)
132
+#define outsw(addr, buffer, count) __outsw(PCI_IOBASE + (addr), buffer, count)
133
+#define outsl(addr, buffer, count) __outsl(PCI_IOBASE + (addr), buffer, count)
284134 
285135 #ifdef CONFIG_64BIT
286
-__io_reads_ins(reads, u64, q, __io_br(), __io_ar())
136
+__io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
287137 #define readsq(addr, buffer, count) __readsq(addr, buffer, count)
288138 
289
-__io_reads_ins(ins, u64, q, __io_pbr(), __io_par())
290
-#define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
139
+__io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
140
+#define insq(addr, buffer, count) __insq(PCI_IOBASE + (addr), buffer, count)
291141 
292142 __io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
293143 #define writesq(addr, buffer, count) __writesq(addr, buffer, count)
294144 
295145 __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
296
-#define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
146
+#define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
297147 #endif
298148 
299149 #include <asm-generic/io.h>