kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/riscv/include/asm/hwcap.h
..
..
@@ -1,24 +1,14 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copied from arch/arm64/include/asm/hwcap.h
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  *
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  * Copyright (C) 2012 ARM Ltd.
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  * Copyright (C) 2017 SiFive
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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-#ifndef __ASM_HWCAP_H
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-#define __ASM_HWCAP_H
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+#ifndef _ASM_RISCV_HWCAP_H
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+#define _ASM_RISCV_HWCAP_H
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10
 
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+#include <linux/bits.h>
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 #include <uapi/asm/hwcap.h>
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13
 
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 #ifndef __ASSEMBLY__
..
..
@@ -33,5 +23,27 @@
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 };
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 extern unsigned long elf_hwcap;
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+
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+#define RISCV_ISA_EXT_a		('a' - 'a')
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+#define RISCV_ISA_EXT_c		('c' - 'a')
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+#define RISCV_ISA_EXT_d		('d' - 'a')
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+#define RISCV_ISA_EXT_f		('f' - 'a')
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+#define RISCV_ISA_EXT_h		('h' - 'a')
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+#define RISCV_ISA_EXT_i		('i' - 'a')
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+#define RISCV_ISA_EXT_m		('m' - 'a')
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+#define RISCV_ISA_EXT_s		('s' - 'a')
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+#define RISCV_ISA_EXT_u		('u' - 'a')
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+
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+#define RISCV_ISA_EXT_MAX	64
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+
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+unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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+
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+#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
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+
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+bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
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+#define riscv_isa_extension_available(isa_bitmap, ext)	\
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+	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
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+
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 #endif
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-#endif
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+
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+#endif /* _ASM_RISCV_HWCAP_H */