.. | .. |
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1080 | 1080 | li r10, -1 |
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1081 | 1081 | mtspr SPRN_DBSR,r10 |
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1082 | 1082 | b restore |
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1083 | | -1: andi. r0,r4,_TIF_NEED_RESCHED_MASK |
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| 1083 | +1: andi. r0,r4,_TIF_NEED_RESCHED |
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1084 | 1084 | beq 2f |
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1085 | 1085 | bl restore_interrupts |
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1086 | 1086 | SCHEDULE_USER |
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.. | .. |
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1132 | 1132 | bne- 0b |
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1133 | 1133 | 1: |
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1134 | 1134 | |
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1135 | | -#ifdef CONFIG_PREEMPTION |
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| 1135 | +#ifdef CONFIG_PREEMPT |
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1136 | 1136 | /* Check if we need to preempt */ |
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1137 | | - lwz r8,TI_PREEMPT(r9) |
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1138 | | - cmpwi 0,r8,0 /* if non-zero, just restore regs and return */ |
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1139 | | - bne restore |
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1140 | 1137 | andi. r0,r4,_TIF_NEED_RESCHED |
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1141 | | - bne+ check_count |
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1142 | | - |
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1143 | | - andi. r0,r4,_TIF_NEED_RESCHED_LAZY |
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1144 | 1138 | beq+ restore |
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1145 | | - lwz r8,TI_PREEMPT_LAZY(r9) |
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1146 | | - |
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1147 | 1139 | /* Check that preempt_count() == 0 and interrupts are enabled */ |
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1148 | | -check_count: |
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| 1140 | + lwz r8,TI_PREEMPT(r9) |
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1149 | 1141 | cmpwi cr0,r8,0 |
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1150 | 1142 | bne restore |
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1151 | 1143 | ld r0,SOFTE(r1) |
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.. | .. |
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1166 | 1158 | * interrupted after loading SRR0/1. |
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1167 | 1159 | */ |
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1168 | 1160 | wrteei 0 |
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1169 | | -#endif /* CONFIG_PREEMPTION */ |
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| 1161 | +#endif /* CONFIG_PREEMPT */ |
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1170 | 1162 | |
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1171 | 1163 | restore: |
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1172 | 1164 | /* |
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