kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/powerpc/include/asm/nohash/pte-book3e.h
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@@ -60,13 +60,8 @@
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 #define _PAGE_SPECIAL	_PAGE_SW0
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 /* Base page size */
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-#ifdef CONFIG_PPC_64K_PAGES
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-#define _PAGE_PSIZE	_PAGE_PSIZE_64K
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-#define PTE_RPN_SHIFT	(28)
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-#else
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 #define _PAGE_PSIZE	_PAGE_PSIZE_4K
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 #define	PTE_RPN_SHIFT	(24)
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-#endif
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 #define PTE_WIMGE_SHIFT (19)
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 #define PTE_BAP_SHIFT	(2)
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@@ -77,7 +72,48 @@
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 #define _PMD_PRESENT	0
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 #define _PMD_PRESENT_MASK (PAGE_MASK)
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 #define _PMD_BAD	(~PAGE_MASK)
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+#define _PMD_USER	0
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+#else
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+#define _PTE_NONE_MASK	0
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 #endif
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+/*
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+ * We define 2 sets of base prot bits, one for basic pages (ie,
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+ * cacheable kernel and user pages) and one for non cacheable
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+ * pages. We always set _PAGE_COHERENT when SMP is enabled or
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+ * the processor might need it for DMA coherency.
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+ */
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+#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
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+#if defined(CONFIG_SMP)
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+#define _PAGE_BASE	(_PAGE_BASE_NC | _PAGE_COHERENT)
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+#else
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+#define _PAGE_BASE	(_PAGE_BASE_NC)
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+#endif
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+
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+/* Permission masks used to generate the __P and __S table */
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+#define PAGE_NONE	__pgprot(_PAGE_BASE)
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+#define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
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+#define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
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+#define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
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+#define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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+#define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
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+#define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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+
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+#ifndef __ASSEMBLY__
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+static inline pte_t pte_mkprivileged(pte_t pte)
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+{
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+	return __pte((pte_val(pte) & ~_PAGE_USER) | _PAGE_PRIVILEGED);
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+}
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+
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+#define pte_mkprivileged pte_mkprivileged
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+
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+static inline pte_t pte_mkuser(pte_t pte)
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+{
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+	return __pte((pte_val(pte) & ~_PAGE_PRIVILEGED) | _PAGE_USER);
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+}
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+
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+#define pte_mkuser pte_mkuser
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+#endif /* __ASSEMBLY__ */
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+
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 #endif /* __KERNEL__ */
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 #endif /*  _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */