.. | .. |
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94 | 94 | cpu0: PowerPC,e500mc@0 { |
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95 | 95 | device_type = "cpu"; |
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96 | 96 | reg = <0>; |
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97 | | - clocks = <&mux0>; |
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| 97 | + clocks = <&clockgen 1 0>; |
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98 | 98 | next-level-cache = <&L2_0>; |
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99 | 99 | fsl,portid-mapping = <0x80000000>; |
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100 | 100 | L2_0: l2-cache { |
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.. | .. |
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104 | 104 | cpu1: PowerPC,e500mc@1 { |
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105 | 105 | device_type = "cpu"; |
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106 | 106 | reg = <1>; |
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107 | | - clocks = <&mux1>; |
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| 107 | + clocks = <&clockgen 1 1>; |
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108 | 108 | next-level-cache = <&L2_1>; |
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109 | 109 | fsl,portid-mapping = <0x40000000>; |
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110 | 110 | L2_1: l2-cache { |
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.. | .. |
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114 | 114 | cpu2: PowerPC,e500mc@2 { |
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115 | 115 | device_type = "cpu"; |
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116 | 116 | reg = <2>; |
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117 | | - clocks = <&mux2>; |
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| 117 | + clocks = <&clockgen 1 2>; |
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118 | 118 | next-level-cache = <&L2_2>; |
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119 | 119 | fsl,portid-mapping = <0x20000000>; |
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120 | 120 | L2_2: l2-cache { |
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.. | .. |
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124 | 124 | cpu3: PowerPC,e500mc@3 { |
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125 | 125 | device_type = "cpu"; |
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126 | 126 | reg = <3>; |
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127 | | - clocks = <&mux3>; |
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| 127 | + clocks = <&clockgen 1 3>; |
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128 | 128 | next-level-cache = <&L2_3>; |
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129 | 129 | fsl,portid-mapping = <0x10000000>; |
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130 | 130 | L2_3: l2-cache { |
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.. | .. |
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134 | 134 | cpu4: PowerPC,e500mc@4 { |
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135 | 135 | device_type = "cpu"; |
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136 | 136 | reg = <4>; |
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137 | | - clocks = <&mux4>; |
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| 137 | + clocks = <&clockgen 1 4>; |
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138 | 138 | next-level-cache = <&L2_4>; |
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139 | 139 | fsl,portid-mapping = <0x08000000>; |
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140 | 140 | L2_4: l2-cache { |
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.. | .. |
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144 | 144 | cpu5: PowerPC,e500mc@5 { |
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145 | 145 | device_type = "cpu"; |
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146 | 146 | reg = <5>; |
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147 | | - clocks = <&mux5>; |
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| 147 | + clocks = <&clockgen 1 5>; |
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148 | 148 | next-level-cache = <&L2_5>; |
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149 | 149 | fsl,portid-mapping = <0x04000000>; |
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150 | 150 | L2_5: l2-cache { |
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.. | .. |
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154 | 154 | cpu6: PowerPC,e500mc@6 { |
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155 | 155 | device_type = "cpu"; |
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156 | 156 | reg = <6>; |
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157 | | - clocks = <&mux6>; |
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| 157 | + clocks = <&clockgen 1 6>; |
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158 | 158 | next-level-cache = <&L2_6>; |
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159 | 159 | fsl,portid-mapping = <0x02000000>; |
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160 | 160 | L2_6: l2-cache { |
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.. | .. |
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164 | 164 | cpu7: PowerPC,e500mc@7 { |
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165 | 165 | device_type = "cpu"; |
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166 | 166 | reg = <7>; |
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167 | | - clocks = <&mux7>; |
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| 167 | + clocks = <&clockgen 1 7>; |
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168 | 168 | next-level-cache = <&L2_7>; |
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169 | 169 | fsl,portid-mapping = <0x01000000>; |
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170 | 170 | L2_7: l2-cache { |
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