kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/mips/ralink/mt7621.c
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..
@@ -1,7 +1,5 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation.
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  *
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  * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
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5
  * Copyright (C) 2015 John Crispin <john@phrozen.org>
..
..
@@ -9,6 +7,8 @@
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7
 
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 #include <linux/kernel.h>
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 #include <linux/init.h>
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+#include <linux/slab.h>
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+#include <linux/sys_soc.h>
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 #include <asm/mipsregs.h>
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 #include <asm/smp-ops.h>
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@@ -19,11 +19,6 @@
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 #include <pinmux.h>
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20
 
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 #include "common.h"
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-
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-#define SYSC_REG_SYSCFG		0x10
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-#define SYSC_REG_CPLL_CLKCFG0	0x2c
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-#define SYSC_REG_CUR_CLK_STS	0x44
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-#define CPU_CLK_SEL		(BIT(30) | BIT(31))
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22
 
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 #define MT7621_GPIO_MODE_UART1		1
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 #define MT7621_GPIO_MODE_I2C		2
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..
@@ -115,44 +110,6 @@
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 	panic("Cannot detect cpc address");
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 }
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112
 
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-void __init ralink_clk_init(void)
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-{
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-	int cpu_fdiv = 0;
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-	int cpu_ffrac = 0;
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-	int fbdiv = 0;
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-	u32 clk_sts, syscfg;
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-	u8 clk_sel = 0, xtal_mode;
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-	u32 cpu_clk;
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-
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-	if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
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-		clk_sel = 1;
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-
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-	switch (clk_sel) {
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-	case 0:
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-		clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
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-		cpu_fdiv = ((clk_sts >> 8) & 0x1F);
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-		cpu_ffrac = (clk_sts & 0x1F);
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-		cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
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-		break;
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-
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-	case 1:
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-		fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
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-		syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
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-		xtal_mode = (syscfg >> 6) & 0x7;
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-		if (xtal_mode >= 6) {
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-			/* 25Mhz Xtal */
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-			cpu_clk = 25 * fbdiv * 1000 * 1000;
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-		} else if (xtal_mode >= 3) {
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-			/* 40Mhz Xtal */
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-			cpu_clk = 40 * fbdiv * 1000 * 1000;
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-		} else {
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-			/* 20Mhz Xtal */
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-			cpu_clk = 20 * fbdiv * 1000 * 1000;
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-		}
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-		break;
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-	}
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-}
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-
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 void __init ralink_of_remap(void)
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 {
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 	rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
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@@ -160,6 +117,33 @@
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117
 
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 	if (!rt_sysc_membase || !rt_memc_membase)
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 		panic("Failed to remap core resources");
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+}
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+
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+static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
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+{
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+	struct soc_device *soc_dev;
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+	struct soc_device_attribute *soc_dev_attr;
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+
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+	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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+	if (!soc_dev_attr)
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+		return;
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+
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+	soc_dev_attr->soc_id = "mt7621";
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+	soc_dev_attr->family = "Ralink";
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+
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+	if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
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+	    (rev & CHIP_REV_ECO_MASK) == 1)
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+		soc_dev_attr->revision = "E2";
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+	else
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+		soc_dev_attr->revision = "E1";
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+
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+	soc_dev_attr->data = soc_info;
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+
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+	soc_dev = soc_device_register(soc_dev_attr);
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+	if (IS_ERR(soc_dev)) {
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+		kfree(soc_dev_attr);
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+		return;
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+	}
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 }
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 void prom_soc_init(struct ralink_soc_info *soc_info)
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@@ -216,6 +200,7 @@
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200
 
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 	rt2880_pinmux_data = mt7621_pinmux_data;
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+	soc_dev_init(soc_info, rev);
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 	if (!register_cps_smp_ops())
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 		return;