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hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/arch/mips/include/asm/cpu-features.h
....@@ -15,6 +15,7 @@
1515 #include <cpu-feature-overrides.h>
1616 
1717 #define __ase(ase)			(cpu_data[0].ases & (ase))
18
+#define __isa(isa)			(cpu_data[0].isa_level & (isa))
1819 #define __opt(opt)			(cpu_data[0].options & (opt))
1920 
2021 /*
....@@ -51,6 +52,20 @@
5152  */
5253 #define __isa_lt_and_ase(isa, ase)	((MIPS_ISA_REV < (isa)) && __ase(ase))
5354 #define __isa_lt_and_opt(isa, opt)	((MIPS_ISA_REV < (isa)) && __opt(opt))
55
+
56
+/*
57
+ * Similarly allow for ISA level checks that take into account knowledge of the
58
+ * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
59
+ */
60
+#define __isa_ge_and_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) && __isa(flag))
61
+#define __isa_ge_or_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) || __isa(flag))
62
+#define __isa_lt_and_flag(isa, flag)	((MIPS_ISA_REV < (isa)) && __isa(flag))
63
+#define __isa_range(ge, lt) \
64
+	((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
65
+#define __isa_range_or_flag(ge, lt, flag) \
66
+	(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
67
+#define __isa_range_and_ase(ge, lt, ase) \
68
+	(__isa_range(ge, lt) && __ase(ase))
5469 
5570 /*
5671  * SMP assumption: Options of CPU 0 are a superset of all processors.
....@@ -115,10 +130,15 @@
115130 #endif
116131 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
117132 #ifndef cpu_has_fpu
118
-#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
119
-#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
133
+# ifdef CONFIG_MIPS_FP_SUPPORT
134
+#  define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
135
+#  define raw_cpu_has_fpu	(raw_current_cpu_data.options & MIPS_CPU_FPU)
136
+# else
137
+#  define cpu_has_fpu		0
138
+#  define raw_cpu_has_fpu	0
139
+# endif
120140 #else
121
-#define raw_cpu_has_fpu		cpu_has_fpu
141
+# define raw_cpu_has_fpu	cpu_has_fpu
122142 #endif
123143 #ifndef cpu_has_32fpr
124144 #define cpu_has_32fpr		__isa_ge_or_opt(1, MIPS_CPU_32FPR)
....@@ -152,9 +172,6 @@
152172 #endif
153173 #ifndef cpu_has_llsc
154174 #define cpu_has_llsc		__isa_ge_or_opt(1, MIPS_CPU_LLSC)
155
-#endif
156
-#ifndef cpu_has_bp_ghist
157
-#define cpu_has_bp_ghist	__opt(MIPS_CPU_BP_GHIST)
158175 #endif
159176 #ifndef kernel_uses_llsc
160177 #define kernel_uses_llsc	cpu_has_llsc
....@@ -195,7 +212,9 @@
195212 #endif
196213 
197214 #ifndef cpu_has_mmips
198
-# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
215
+# if defined(__mips_micromips)
216
+#  define cpu_has_mmips		1
217
+# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
199218 #  define cpu_has_mmips		__opt(MIPS_CPU_MICROMIPS)
200219 # else
201220 #  define cpu_has_mmips		0
....@@ -223,9 +242,6 @@
223242 #ifndef cpu_has_pindexed_dcache
224243 #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
225244 #endif
226
-#ifndef cpu_has_local_ebase
227
-#define cpu_has_local_ebase	1
228
-#endif
229245 
230246 /*
231247  * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
....@@ -246,48 +262,47 @@
246262 #endif
247263 #endif
248264 
249
-/* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */
250
-#if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \
251
-	  (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \
252
-	  (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \
253
-	  (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \
254
-	  (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \
255
-	  (defined(cpu_has_mips64r6) && cpu_has_mips64r6))
256
-#define CPU_NO_EFFICIENT_FFS 1
257
-#endif
258
-
259265 #ifndef cpu_has_mips_1
260
-# define cpu_has_mips_1		(!cpu_has_mips_r6)
266
+# define cpu_has_mips_1		(MIPS_ISA_REV < 6)
261267 #endif
262268 #ifndef cpu_has_mips_2
263
-# define cpu_has_mips_2		(cpu_data[0].isa_level & MIPS_CPU_ISA_II)
269
+# define cpu_has_mips_2		__isa_lt_and_flag(6, MIPS_CPU_ISA_II)
264270 #endif
265271 #ifndef cpu_has_mips_3
266
-# define cpu_has_mips_3		(cpu_data[0].isa_level & MIPS_CPU_ISA_III)
272
+# define cpu_has_mips_3		__isa_lt_and_flag(6, MIPS_CPU_ISA_III)
267273 #endif
268274 #ifndef cpu_has_mips_4
269
-# define cpu_has_mips_4		(cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
275
+# define cpu_has_mips_4		__isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
270276 #endif
271277 #ifndef cpu_has_mips_5
272
-# define cpu_has_mips_5		(cpu_data[0].isa_level & MIPS_CPU_ISA_V)
278
+# define cpu_has_mips_5		__isa_lt_and_flag(6, MIPS_CPU_ISA_V)
273279 #endif
274280 #ifndef cpu_has_mips32r1
275
-# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
281
+# define cpu_has_mips32r1	__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
276282 #endif
277283 #ifndef cpu_has_mips32r2
278
-# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
284
+# define cpu_has_mips32r2	__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
285
+#endif
286
+#ifndef cpu_has_mips32r5
287
+# define cpu_has_mips32r5	__isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
279288 #endif
280289 #ifndef cpu_has_mips32r6
281
-# define cpu_has_mips32r6	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
290
+# define cpu_has_mips32r6	__isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
282291 #endif
283292 #ifndef cpu_has_mips64r1
284
-# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
293
+# define cpu_has_mips64r1	(cpu_has_64bits && \
294
+				 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
285295 #endif
286296 #ifndef cpu_has_mips64r2
287
-# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
297
+# define cpu_has_mips64r2	(cpu_has_64bits && \
298
+				 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
299
+#endif
300
+#ifndef cpu_has_mips64r5
301
+# define cpu_has_mips64r5	(cpu_has_64bits && \
302
+				 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
288303 #endif
289304 #ifndef cpu_has_mips64r6
290
-# define cpu_has_mips64r6	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
305
+# define cpu_has_mips64r6	__isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
291306 #endif
292307 
293308 /*
....@@ -306,19 +321,25 @@
306321 				(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
307322 #define cpu_has_mips_4_5_64_r2_r6					\
308323 				(cpu_has_mips_4_5 | cpu_has_mips64r1 |	\
309
-				 cpu_has_mips_r2 | cpu_has_mips_r6)
324
+				 cpu_has_mips_r2 | cpu_has_mips_r5 | \
325
+				 cpu_has_mips_r6)
310326 
311
-#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
312
-#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
327
+#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
328
+			 cpu_has_mips32r5 | cpu_has_mips32r6)
329
+#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | \
330
+			 cpu_has_mips64r5 | cpu_has_mips64r6)
313331 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
314332 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
333
+#define cpu_has_mips_r5	(cpu_has_mips32r5 | cpu_has_mips64r5)
315334 #define cpu_has_mips_r6	(cpu_has_mips32r6 | cpu_has_mips64r6)
316335 #define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
317
-			 cpu_has_mips32r6 | cpu_has_mips64r1 | \
318
-			 cpu_has_mips64r2 | cpu_has_mips64r6)
336
+			 cpu_has_mips32r5 | cpu_has_mips32r6 | \
337
+			 cpu_has_mips64r1 | cpu_has_mips64r2 | \
338
+			 cpu_has_mips64r5 | cpu_has_mips64r6)
319339 
320
-/* MIPSR2 and MIPSR6 have a lot of similarities */
321
-#define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r6)
340
+/* MIPSR2 - MIPSR6 have a lot of similarities */
341
+#define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r5 | \
342
+				 cpu_has_mips_r6)
322343 
323344 /*
324345  * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
....@@ -404,7 +425,7 @@
404425 #endif
405426 
406427 #ifndef cpu_has_mipsmt
407
-#define cpu_has_mipsmt		__isa_lt_and_ase(6, MIPS_ASE_MIPSMT)
428
+#define cpu_has_mipsmt		__isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
408429 #endif
409430 
410431 #ifndef cpu_has_vp
....@@ -428,9 +449,6 @@
428449 # ifndef cpu_has_64bit_gp_regs
429450 # define cpu_has_64bit_gp_regs		0
430451 # endif
431
-# ifndef cpu_has_64bit_addresses
432
-# define cpu_has_64bit_addresses	0
433
-# endif
434452 # ifndef cpu_vmbits
435453 # define cpu_vmbits 31
436454 # endif
....@@ -448,9 +466,6 @@
448466 # endif
449467 # ifndef cpu_has_64bit_gp_regs
450468 # define cpu_has_64bit_gp_regs		1
451
-# endif
452
-# ifndef cpu_has_64bit_addresses
453
-# define cpu_has_64bit_addresses	1
454469 # endif
455470 # ifndef cpu_vmbits
456471 # define cpu_vmbits cpu_data[0].vmbits
....@@ -548,6 +563,18 @@
548563 # define cpu_has_perf		__opt(MIPS_CPU_PERF)
549564 #endif
550565 
566
+#ifndef cpu_has_mac2008_only
567
+# define cpu_has_mac2008_only	__opt(MIPS_CPU_MAC_2008_ONLY)
568
+#endif
569
+
570
+#ifndef cpu_has_ftlbparex
571
+# define cpu_has_ftlbparex	__opt(MIPS_CPU_FTLBPAREX)
572
+#endif
573
+
574
+#ifndef cpu_has_gsexcex
575
+# define cpu_has_gsexcex	__opt(MIPS_CPU_GSEXCEX)
576
+#endif
577
+
551578 #ifdef CONFIG_SMP
552579 /*
553580  * Some systems share FTLB RAMs between threads within a core (siblings in
....@@ -597,6 +624,27 @@
597624 #endif /* CONFIG_MIPS_MT_SMP */
598625 
599626 /*
627
+ * We only enable MMID support for configurations which natively support 64 bit
628
+ * atomics because getting good performance from the allocator relies upon
629
+ * efficient atomic64_*() functions.
630
+ */
631
+#ifndef cpu_has_mmid
632
+# ifdef CONFIG_GENERIC_ATOMIC64
633
+#  define cpu_has_mmid		0
634
+# else
635
+#  define cpu_has_mmid		__isa_ge_and_opt(6, MIPS_CPU_MMID)
636
+# endif
637
+#endif
638
+
639
+#ifndef cpu_has_mm_sysad
640
+# define cpu_has_mm_sysad	__opt(MIPS_CPU_MM_SYSAD)
641
+#endif
642
+
643
+#ifndef cpu_has_mm_full
644
+# define cpu_has_mm_full	__opt(MIPS_CPU_MM_FULL)
645
+#endif
646
+
647
+/*
600648  * Guest capabilities
601649  */
602650 #ifndef cpu_guest_has_conf1
....@@ -641,6 +689,9 @@
641689 #ifndef cpu_guest_has_htw
642690 #define cpu_guest_has_htw	(cpu_data[0].guest.options & MIPS_CPU_HTW)
643691 #endif
692
+#ifndef cpu_guest_has_ldpte
693
+#define cpu_guest_has_ldpte	(cpu_data[0].guest.options & MIPS_CPU_LDPTE)
694
+#endif
644695 #ifndef cpu_guest_has_mvh
645696 #define cpu_guest_has_mvh	(cpu_data[0].guest.options & MIPS_CPU_MVH)
646697 #endif