~hc/RK356X_SDK_RELEASE.git

..	..	@@ -279,9 +279,39 @@
279	279	#define MCFGPIO_PIN_MAX 87
280	280
281	281	/*
	282	+ * Phase Locked Loop (PLL)
	283	+ */
	284	+#define MCF_PLL_CR 0xFC0C0000
	285	+#define MCF_PLL_DR 0xFC0C0004
	286	+#define MCF_PLL_SR 0xFC0C0008
	287	+
	288	+/*
282	289	* DSPI module.
283	290	*/
284	291	#define MCFDSPI_BASE0 0xfc05c000
	292	+#define MCFDSPI_BASE1 0xfC03c000
285	293	#define MCF_IRQ_DSPI0 (MCFINT0_VECBASE + MCFINT0_DSPI0)
	294	+#define MCF_IRQ_DSPI1 (MCFINT1_VECBASE + MCFINT1_DSPI1)
	295	+/*
	296	+ * eDMA module.
	297	+ */
	298	+#define MCFEDMA_BASE 0xfc044000
	299	+#define MCFEDMA_SIZE 0x4000
	300	+#define MCFINT0_EDMA_INTR0 8
	301	+#define MCFINT0_EDMA_ERR 24
	302	+#define MCFEDMA_EDMA_INTR16 8
	303	+#define MCFEDMA_EDMA_INTR56 0
	304	+#define MCFEDMA_IRQ_INTR0 (MCFINT0_VECBASE + MCFINT0_EDMA_INTR0)
	305	+#define MCFEDMA_IRQ_INTR16 (MCFINT1_VECBASE + MCFEDMA_EDMA_INTR16)
	306	+#define MCFEDMA_IRQ_INTR56 (MCFINT2_VECBASE + MCFEDMA_EDMA_INTR56)
	307	+#define MCFEDMA_IRQ_ERR (MCFINT0_VECBASE + MCFINT0_EDMA_ERR)
	308	+/*
	309	+ * esdhc module.
	310	+ */
	311	+#define MCFSDHC_BASE 0xfc0cc000
	312	+#define MCFSDHC_SIZE 256
	313	+#define MCFINT2_SDHC 31
	314	+#define MCF_IRQ_SDHC (MCFINT2_VECBASE + MCFINT2_SDHC)
	315	+#define MCFSDHC_CLK (MCFSDHC_BASE + 0x2c)
286	316
287	317	#endif /* m5441xsim_h */