kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/m68k/coldfire/m5441x.c
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@@ -52,7 +52,7 @@
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 DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
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 DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
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 DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
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-DEFINE_CLK(0, "mcfsdhc.0", 51, MCF_CLK);
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+DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
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 DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
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 DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
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 DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
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@@ -73,6 +73,10 @@
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 DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
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 DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
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 DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
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+
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+DEFINE_CLK(2, "ipg.0", 0, MCF_CLK);
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+DEFINE_CLK(2, "ahb.0", 1, MCF_CLK);
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+DEFINE_CLK(2, "per.0", 2, MCF_CLK);
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80
 
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 struct clk *mcf_clks[] = {
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 	&__clk_0_2,
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@@ -131,12 +135,19 @@
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 	&__clk_1_34,
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 	&__clk_1_36,
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 	&__clk_1_37,
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+
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+	&__clk_2_0,
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+	&__clk_2_1,
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+	&__clk_2_2,
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+
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 	NULL,
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 };
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 static struct clk * const enable_clks[] __initconst = {
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 	/* make sure these clocks are enabled */
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+	&__clk_0_15, /* dspi.1 */
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+	&__clk_0_17, /* eDMA */
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 	&__clk_0_18, /* intc0 */
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 	&__clk_0_19, /* intc0 */
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 	&__clk_0_20, /* intc0 */
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@@ -149,6 +160,7 @@
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 	&__clk_0_33, /* pit.1 */
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 	&__clk_0_37, /* eport */
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 	&__clk_0_48, /* pll */
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+	&__clk_0_51, /* esdhc */
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 	&__clk_1_36, /* CCM/reset module/Power management */
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 	&__clk_1_37, /* gpio */
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@@ -157,8 +169,6 @@
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 	&__clk_0_8, /* can.0 */
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 	&__clk_0_9, /* can.1 */
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 	&__clk_0_14, /* i2c.1 */
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-	&__clk_0_15, /* dspi.1 */
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-	&__clk_0_17, /* eDMA */
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 	&__clk_0_22, /* i2c.0 */
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 	&__clk_0_23, /* dspi.0 */
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 	&__clk_0_28, /* tmr.1 */
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@@ -194,6 +204,21 @@
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 	&__clk_1_29, /* uart 9 */
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 };
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+static void __clk_enable2(struct clk *clk)
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+{
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+	__raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
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+}
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+
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+static void __clk_disable2(struct clk *clk)
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+{
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+	__raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
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+}
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+
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+struct clk_ops clk_ops2 = {
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+	.enable		= __clk_enable2,
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+	.disable	= __clk_disable2,
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+};
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+
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 static void __init m5441x_clk_init(void)
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 {
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 	unsigned i;