kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm64/kvm/fpsimd.c
..
..
@@ -9,8 +9,9 @@
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9
 #include <linux/sched.h>
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10
 #include <linux/thread_info.h>
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11
 #include <linux/kvm_host.h>
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+#include <asm/fpsimd.h>
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 #include <asm/kvm_asm.h>
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-#include <asm/kvm_host.h>
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+#include <asm/kvm_hyp.h>
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 #include <asm/kvm_mmu.h>
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 #include <asm/sysreg.h>
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17
 
..
..
@@ -41,6 +42,17 @@
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 	ret = create_hyp_mappings(fpsimd, fpsimd + 1, PAGE_HYP);
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 	if (ret)
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 		goto error;
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+
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+	if (vcpu->arch.sve_state) {
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+		void *sve_end;
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+
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+		sve_end = vcpu->arch.sve_state + vcpu_sve_state_size(vcpu);
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+
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+		ret = create_hyp_mappings(vcpu->arch.sve_state, sve_end,
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+					  PAGE_HYP);
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+		if (ret)
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+			goto error;
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+	}
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56
 
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 	vcpu->arch.host_thread_info = kern_hyp_va(ti);
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58
 	vcpu->arch.host_fpsimd_state = kern_hyp_va(fpsimd);
..
..
@@ -85,9 +97,12 @@
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 	WARN_ON_ONCE(!irqs_disabled());
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98
 
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 	if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) {
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-		fpsimd_bind_state_to_cpu(&vcpu->arch.ctxt.gp_regs.fp_regs);
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+		fpsimd_bind_state_to_cpu(&vcpu->arch.ctxt.fp_regs,
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+					 vcpu->arch.sve_state,
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+					 vcpu->arch.sve_max_vl);
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+
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 		clear_thread_flag(TIF_FOREIGN_FPSTATE);
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-		clear_thread_flag(TIF_SVE);
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+		update_thread_flag(TIF_SVE, vcpu_has_sve(vcpu));
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106
 	}
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107
 }
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108
 
..
..
@@ -100,14 +115,23 @@
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 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu)
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 {
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117
 	unsigned long flags;
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+	bool host_has_sve = system_supports_sve();
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+	bool guest_has_sve = vcpu_has_sve(vcpu);
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120
 
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 	local_irq_save(flags);
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122
 
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 	if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) {
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-		/* Clean guest FP state to memory and invalidate cpu view */
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-		fpsimd_save();
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-		fpsimd_flush_cpu_state();
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-	} else if (system_supports_sve()) {
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+		if (guest_has_sve) {
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+			__vcpu_sys_reg(vcpu, ZCR_EL1) = read_sysreg_el1(SYS_ZCR);
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+
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+			/* Restore the VL that was saved when bound to the CPU */
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+			if (!has_vhe())
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+				sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1,
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+						       SYS_ZCR_EL1);
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+		}
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+
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+		fpsimd_save_and_flush_cpu_state();
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+	} else if (has_vhe() && host_has_sve) {
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135
 		/*
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 		 * The FPSIMD/SVE state in the CPU has not been touched, and we
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137
 		 * have SVE (and VHE): CPACR_EL1 (alias CPTR_EL2) has been