kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm64/include/asm/perf_event.h
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@@ -1,17 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (C) 2012 ARM Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #ifndef __ASM_PERF_EVENT_H
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@@ -24,6 +13,187 @@
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 #define	ARMV8_PMU_COUNTER_MASK	(ARMV8_PMU_MAX_COUNTERS - 1)
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 /*
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+ * Common architectural and microarchitectural event numbers.
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+ */
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+#define ARMV8_PMUV3_PERFCTR_SW_INCR				0x00
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+#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL			0x01
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+#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL			0x02
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+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL			0x03
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+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE				0x04
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+#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL			0x05
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+#define ARMV8_PMUV3_PERFCTR_LD_RETIRED				0x06
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+#define ARMV8_PMUV3_PERFCTR_ST_RETIRED				0x07
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+#define ARMV8_PMUV3_PERFCTR_INST_RETIRED			0x08
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+#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN				0x09
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+#define ARMV8_PMUV3_PERFCTR_EXC_RETURN				0x0A
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+#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED			0x0B
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+#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED			0x0C
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+#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED			0x0D
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+#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED			0x0E
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+#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED		0x0F
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+#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED				0x10
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+#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES				0x11
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+#define ARMV8_PMUV3_PERFCTR_BR_PRED				0x12
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+#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS				0x13
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+#define ARMV8_PMUV3_PERFCTR_L1I_CACHE				0x14
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+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB			0x15
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+#define ARMV8_PMUV3_PERFCTR_L2D_CACHE				0x16
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+#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL			0x17
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+#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB			0x18
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+#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS				0x19
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+#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR			0x1A
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+#define ARMV8_PMUV3_PERFCTR_INST_SPEC				0x1B
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+#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED			0x1C
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+#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES				0x1D
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+#define ARMV8_PMUV3_PERFCTR_CHAIN				0x1E
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+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE			0x1F
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+#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE			0x20
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+#define ARMV8_PMUV3_PERFCTR_BR_RETIRED				0x21
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+#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED			0x22
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+#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND			0x23
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+#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND			0x24
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+#define ARMV8_PMUV3_PERFCTR_L1D_TLB				0x25
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+#define ARMV8_PMUV3_PERFCTR_L1I_TLB				0x26
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+#define ARMV8_PMUV3_PERFCTR_L2I_CACHE				0x27
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+#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL			0x28
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+#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE			0x29
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+#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL			0x2A
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+#define ARMV8_PMUV3_PERFCTR_L3D_CACHE				0x2B
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+#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB			0x2C
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+#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL			0x2D
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+#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL			0x2E
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+#define ARMV8_PMUV3_PERFCTR_L2D_TLB				0x2F
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+#define ARMV8_PMUV3_PERFCTR_L2I_TLB				0x30
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+#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS			0x31
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+#define ARMV8_PMUV3_PERFCTR_LL_CACHE				0x32
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+#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS			0x33
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+#define ARMV8_PMUV3_PERFCTR_DTLB_WALK				0x34
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+#define ARMV8_PMUV3_PERFCTR_ITLB_WALK				0x35
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+#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD				0x36
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+#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD			0x37
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+#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD			0x38
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+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD			0x39
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+#define ARMV8_PMUV3_PERFCTR_OP_RETIRED				0x3A
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+#define ARMV8_PMUV3_PERFCTR_OP_SPEC				0x3B
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+#define ARMV8_PMUV3_PERFCTR_STALL				0x3C
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+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND			0x3D
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+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND			0x3E
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+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT				0x3F
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+
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+/* Statistical profiling extension microarchitectural events */
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+#define	ARMV8_SPE_PERFCTR_SAMPLE_POP				0x4000
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+#define	ARMV8_SPE_PERFCTR_SAMPLE_FEED				0x4001
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+#define	ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE			0x4002
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+#define	ARMV8_SPE_PERFCTR_SAMPLE_COLLISION			0x4003
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+
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+/* AMUv1 architecture events */
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+#define	ARMV8_AMU_PERFCTR_CNT_CYCLES				0x4004
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+#define	ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM			0x4005
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+
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+/* long-latency read miss events */
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+#define	ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS			0x4006
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+#define	ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD			0x4009
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+#define	ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS			0x400A
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+#define	ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD			0x400B
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+
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+/* additional latency from alignment events */
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+#define	ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT			0x4020
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+#define	ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT			0x4021
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+#define	ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT			0x4022
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+
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+/* Armv8.5 Memory Tagging Extension events */
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+#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED			0x4024
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+#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD			0x4025
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+#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR			0x4026
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+
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+/* ARMv8 recommended implementation defined event types */
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD			0x40
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR			0x41
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD		0x42
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR		0x43
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER		0x44
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER		0x45
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM		0x46
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN			0x47
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+#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL			0x48
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+
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+#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD			0x4C
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+#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR			0x4D
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+#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD				0x4E
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+#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR				0x4F
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+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD			0x50
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+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR			0x51
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+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD		0x52
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+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR		0x53
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+
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+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM		0x56
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+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN			0x57
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+#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL			0x58
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+
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+#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD			0x5C
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+#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR			0x5D
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+#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD				0x5E
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+#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR				0x5F
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+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD			0x60
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+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR			0x61
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+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED			0x62
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+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED		0x63
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+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL			0x64
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+#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH			0x65
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+#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD			0x66
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+#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR			0x67
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+#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC			0x68
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+#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC			0x69
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+#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC		0x6A
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+
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+#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC				0x6C
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+#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC			0x6D
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+#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC			0x6E
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+#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC				0x6F
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+#define ARMV8_IMPDEF_PERFCTR_LD_SPEC				0x70
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+#define ARMV8_IMPDEF_PERFCTR_ST_SPEC				0x71
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+#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC				0x72
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+#define ARMV8_IMPDEF_PERFCTR_DP_SPEC				0x73
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+#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC				0x74
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+#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC				0x75
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+#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC			0x76
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+#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC			0x77
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+#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC			0x78
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+#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC			0x79
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+#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC			0x7A
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+
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+#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC				0x7C
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+#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC				0x7D
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+#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC				0x7E
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+
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+#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF				0x81
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+#define ARMV8_IMPDEF_PERFCTR_EXC_SVC				0x82
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+#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT				0x83
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+#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT				0x84
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+
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+#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ				0x86
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+#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ				0x87
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+#define ARMV8_IMPDEF_PERFCTR_EXC_SMC				0x88
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+
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+#define ARMV8_IMPDEF_PERFCTR_EXC_HVC				0x8A
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+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT			0x8B
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+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT			0x8C
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+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER			0x8D
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+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ			0x8E
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+#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ			0x8F
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+#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC				0x90
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+#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC				0x91
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+
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+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD			0xA0
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+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR			0xA1
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+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD		0xA2
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+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR		0xA3
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+
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+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM		0xA6
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+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN			0xA7
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+#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL			0xA8
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+
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+/*
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  * Per-CPU PMCR: config reg
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  */
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 #define ARMV8_PMU_PMCR_E	(1 << 0) /* Enable all counters */
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@@ -33,9 +203,10 @@
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 #define ARMV8_PMU_PMCR_X	(1 << 4) /* Export to ETM */
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 #define ARMV8_PMU_PMCR_DP	(1 << 5) /* Disable CCNT if non-invasive debug*/
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 #define ARMV8_PMU_PMCR_LC	(1 << 6) /* Overflow on 64 bit cycle counter */
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+#define ARMV8_PMU_PMCR_LP	(1 << 7) /* Long event counter enable */
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 #define	ARMV8_PMU_PMCR_N_SHIFT	11	 /* Number of counters supported */
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 #define	ARMV8_PMU_PMCR_N_MASK	0x1f
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-#define	ARMV8_PMU_PMCR_MASK	0x7f	 /* Mask for writable bits */
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+#define	ARMV8_PMU_PMCR_MASK	0xff	 /* Mask for writable bits */
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 /*
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  * PMOVSR: counters overflow flag status reg
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@@ -50,21 +221,11 @@
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 #define	ARMV8_PMU_EVTYPE_EVENT	0xffff		/* Mask for EVENT bits */
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222
 
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 /*
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- * PMUv3 event types: required events
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- */
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-#define ARMV8_PMUV3_PERFCTR_SW_INCR				0x00
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-#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL			0x03
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-#define ARMV8_PMUV3_PERFCTR_L1D_CACHE				0x04
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-#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED				0x10
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-#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES				0x11
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-#define ARMV8_PMUV3_PERFCTR_BR_PRED				0x12
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-
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-/*
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  * Event filters for PMUv3
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  */
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-#define	ARMV8_PMU_EXCLUDE_EL1	(1 << 31)
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-#define	ARMV8_PMU_EXCLUDE_EL0	(1 << 30)
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-#define	ARMV8_PMU_INCLUDE_EL2	(1 << 27)
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+#define	ARMV8_PMU_EXCLUDE_EL1	(1U << 31)
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+#define	ARMV8_PMU_EXCLUDE_EL0	(1U << 30)
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+#define	ARMV8_PMU_INCLUDE_EL2	(1U << 27)
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 /*
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  * PMUSERENR: user enable reg
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@@ -75,6 +236,9 @@
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 #define ARMV8_PMU_USERENR_CR	(1 << 2) /* Cycle counter can be read at EL0 */
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 #define ARMV8_PMU_USERENR_ER	(1 << 3) /* Event counter can be read at EL0 */
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+/* PMMIR_EL1.SLOTS mask */
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+#define ARMV8_PMU_SLOTS_MASK	0xff
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+
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 #ifdef CONFIG_PERF_EVENTS
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 struct pt_regs;
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 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);