kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
..
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@@ -2,7 +2,7 @@
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2
 /*
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  * dts file for Xilinx ZynqMP
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  *
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- * (C) Copyright 2014 - 2015, Xilinx, Inc.
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+ * (C) Copyright 2014 - 2019, Xilinx, Inc.
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  *
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7
  * Michal Simek <michal.simek@xilinx.com>
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  *
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@@ -11,6 +11,9 @@
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  * published by the Free Software Foundation; either version 2 of
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  * the License, or (at your option) any later version.
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13
  */
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+
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+#include <dt-bindings/power/xlnx-zynqmp-power.h>
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+#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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17
 
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 / {
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 	compatible = "xlnx,zynqmp";
..
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@@ -22,7 +25,7 @@
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 		#size-cells = <0>;
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26
 
24
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 		cpu0: cpu@0 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
28
+			compatible = "arm,cortex-a53";
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29
 			device_type = "cpu";
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30
 			enable-method = "psci";
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31
 			operating-points-v2 = <&cpu_opp_table>;
..
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@@ -31,7 +34,7 @@
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34
 		};
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35
 
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 		cpu1: cpu@1 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			enable-method = "psci";
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 			reg = <0x1>;
..
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@@ -40,7 +43,7 @@
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43
 		};
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44
 
42
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 		cpu2: cpu@2 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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47
 			device_type = "cpu";
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 			enable-method = "psci";
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 			reg = <0x2>;
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@@ -49,7 +52,7 @@
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 		};
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53
 
51
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 		cpu3: cpu@3 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
55
+			compatible = "arm,cortex-a53";
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56
 			device_type = "cpu";
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57
 			enable-method = "psci";
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 			reg = <0x3>;
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@@ -115,6 +118,53 @@
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 		method = "smc";
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119
 	};
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120
 
121
+	firmware {
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+		zynqmp_firmware: zynqmp-firmware {
123
+			compatible = "xlnx,zynqmp-firmware";
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+			#power-domain-cells = <1>;
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+			method = "smc";
126
+
127
+			zynqmp_power: zynqmp-power {
128
+				compatible = "xlnx,zynqmp-power";
129
+				interrupt-parent = <&gic>;
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+				interrupts = <0 35 4>;
131
+			};
132
+
133
+			zynqmp_clk: clock-controller {
134
+				#clock-cells = <1>;
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+				compatible = "xlnx,zynqmp-clk";
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+				clocks = <&pss_ref_clk>,
137
+					 <&video_clk>,
138
+					 <&pss_alt_ref_clk>,
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+					 <&aux_ref_clk>,
140
+					 <&gt_crx_ref_clk>;
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+				clock-names = "pss_ref_clk",
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+					      "video_clk",
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+					      "pss_alt_ref_clk",
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+					      "aux_ref_clk",
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+					      "gt_crx_ref_clk";
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+			};
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+
148
+			nvmem_firmware {
149
+				compatible = "xlnx,zynqmp-nvmem-fw";
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+				#address-cells = <1>;
151
+				#size-cells = <1>;
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+
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+				soc_revision: soc_revision@0 {
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+					reg = <0x0 0x4>;
155
+				};
156
+			};
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+
158
+			zynqmp_pcap: pcap {
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+				compatible = "xlnx,zynqmp-pcap-fpga";
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+			};
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+
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+			xlnx_aes: zynqmp-aes {
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+				compatible = "xlnx,zynqmp-aes";
164
+			};
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+		};
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+	};
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+
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 	timer {
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 		compatible = "arm,armv8-timer";
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 		interrupt-parent = <&gic>;
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@@ -124,14 +174,22 @@
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 			     <1 10 0xf08>;
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 	};
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-	amba_apu: amba-apu@0 {
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+	fpga_full: fpga-full {
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+		compatible = "fpga-region";
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+		fpga-mgr = <&zynqmp_pcap>;
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+		#address-cells = <2>;
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+		#size-cells = <2>;
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+		ranges;
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+	};
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+
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+	amba_apu: axi@0 {
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 		compatible = "simple-bus";
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 		#address-cells = <2>;
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 		#size-cells = <1>;
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 		ranges = <0 0 0 0 0xffffffff>;
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 		gic: interrupt-controller@f9010000 {
134
-			compatible = "arm,gic-400", "arm,cortex-a15-gic";
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+			compatible = "arm,gic-400";
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 			#interrupt-cells = <3>;
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 			reg = <0x0 0xf9010000 0x10000>,
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 			      <0x0 0xf9020000 0x20000>,
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@@ -143,7 +201,7 @@
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 		};
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 	};
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-	amba: amba {
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+	amba: axi {
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 		compatible = "simple-bus";
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 		#address-cells = <2>;
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 		#size-cells = <2>;
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@@ -158,6 +216,7 @@
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 			interrupt-parent = <&gic>;
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 			tx-fifo-depth = <0x40>;
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 			rx-fifo-depth = <0x40>;
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+			power-domains = <&zynqmp_firmware PD_CAN_0>;
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 		};
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 		can1: can@ff070000 {
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@@ -169,6 +228,7 @@
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 			interrupt-parent = <&gic>;
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 			tx-fifo-depth = <0x40>;
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 			rx-fifo-depth = <0x40>;
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+			power-domains = <&zynqmp_firmware PD_CAN_1>;
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 		};
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 		cci: cci@fd6e0000 {
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@@ -199,6 +259,7 @@
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 			interrupts = <0 124 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <128>;
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+			power-domains = <&zynqmp_firmware PD_GDMA>;
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 		};
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264
 
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 		fpd_dma_chan2: dma@fd510000 {
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@@ -209,6 +270,7 @@
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 			interrupts = <0 125 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <128>;
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+			power-domains = <&zynqmp_firmware PD_GDMA>;
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 		};
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 		fpd_dma_chan3: dma@fd520000 {
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@@ -219,6 +281,7 @@
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 			interrupts = <0 126 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <128>;
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+			power-domains = <&zynqmp_firmware PD_GDMA>;
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 		};
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286
 
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 		fpd_dma_chan4: dma@fd530000 {
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@@ -229,6 +292,7 @@
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 			interrupts = <0 127 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <128>;
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+			power-domains = <&zynqmp_firmware PD_GDMA>;
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 		};
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 		fpd_dma_chan5: dma@fd540000 {
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@@ -239,6 +303,7 @@
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 			interrupts = <0 128 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <128>;
306
+			power-domains = <&zynqmp_firmware PD_GDMA>;
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 		};
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308
 
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 		fpd_dma_chan6: dma@fd550000 {
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@@ -249,6 +314,7 @@
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 			interrupts = <0 129 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <128>;
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+			power-domains = <&zynqmp_firmware PD_GDMA>;
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 		};
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 		fpd_dma_chan7: dma@fd560000 {
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@@ -259,6 +325,7 @@
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 			interrupts = <0 130 4>;
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 			clock-names = "clk_main", "clk_apb";
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327
 			xlnx,bus-width = <128>;
328
+			power-domains = <&zynqmp_firmware PD_GDMA>;
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329
 		};
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330
 
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 		fpd_dma_chan8: dma@fd570000 {
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@@ -269,6 +336,7 @@
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 			interrupts = <0 131 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <128>;
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+			power-domains = <&zynqmp_firmware PD_GDMA>;
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 		};
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 		/* LPDDMA default allows only secured access. inorder to enable
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@@ -283,6 +351,7 @@
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 			interrupts = <0 77 4>;
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 			clock-names = "clk_main", "clk_apb";
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353
 			xlnx,bus-width = <64>;
354
+			power-domains = <&zynqmp_firmware PD_ADMA>;
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355
 		};
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356
 
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 		lpd_dma_chan2: dma@ffa90000 {
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@@ -293,6 +362,7 @@
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 			interrupts = <0 78 4>;
294
363
 			clock-names = "clk_main", "clk_apb";
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364
 			xlnx,bus-width = <64>;
365
+			power-domains = <&zynqmp_firmware PD_ADMA>;
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366
 		};
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367
 
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 		lpd_dma_chan3: dma@ffaa0000 {
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@@ -303,6 +373,7 @@
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 			interrupts = <0 79 4>;
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 			clock-names = "clk_main", "clk_apb";
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375
 			xlnx,bus-width = <64>;
376
+			power-domains = <&zynqmp_firmware PD_ADMA>;
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377
 		};
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378
 
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 		lpd_dma_chan4: dma@ffab0000 {
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@@ -313,6 +384,7 @@
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 			interrupts = <0 80 4>;
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 			clock-names = "clk_main", "clk_apb";
315
386
 			xlnx,bus-width = <64>;
387
+			power-domains = <&zynqmp_firmware PD_ADMA>;
316
388
 		};
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389
 
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 		lpd_dma_chan5: dma@ffac0000 {
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@@ -323,6 +395,7 @@
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 			interrupts = <0 81 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <64>;
398
+			power-domains = <&zynqmp_firmware PD_ADMA>;
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 		};
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 		lpd_dma_chan6: dma@ffad0000 {
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@@ -333,6 +406,7 @@
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 			interrupts = <0 82 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <64>;
409
+			power-domains = <&zynqmp_firmware PD_ADMA>;
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 		};
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 		lpd_dma_chan7: dma@ffae0000 {
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@@ -343,6 +417,7 @@
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 			interrupts = <0 83 4>;
344
418
 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <64>;
420
+			power-domains = <&zynqmp_firmware PD_ADMA>;
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421
 		};
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422
 
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 		lpd_dma_chan8: dma@ffaf0000 {
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@@ -353,6 +428,14 @@
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 			interrupts = <0 84 4>;
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 			clock-names = "clk_main", "clk_apb";
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 			xlnx,bus-width = <64>;
431
+			power-domains = <&zynqmp_firmware PD_ADMA>;
432
+		};
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+
434
+		mc: memory-controller@fd070000 {
435
+			compatible = "xlnx,zynqmp-ddrc-2.40a";
436
+			reg = <0x0 0xfd070000 0x0 0x30000>;
437
+			interrupt-parent = <&gic>;
438
+			interrupts = <0 112 4>;
356
439
 		};
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440
 
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 		gem0: ethernet@ff0b0000 {
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@@ -364,6 +447,7 @@
364
447
 			clock-names = "pclk", "hclk", "tx_clk";
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 			#address-cells = <1>;
366
449
 			#size-cells = <0>;
450
+			power-domains = <&zynqmp_firmware PD_ETH_0>;
367
451
 		};
368
452
 
369
453
 		gem1: ethernet@ff0c0000 {
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@@ -375,6 +459,7 @@
375
459
 			clock-names = "pclk", "hclk", "tx_clk";
376
460
 			#address-cells = <1>;
377
461
 			#size-cells = <0>;
462
+			power-domains = <&zynqmp_firmware PD_ETH_1>;
378
463
 		};
379
464
 
380
465
 		gem2: ethernet@ff0d0000 {
..
..
@@ -386,6 +471,7 @@
386
471
 			clock-names = "pclk", "hclk", "tx_clk";
387
472
 			#address-cells = <1>;
388
473
 			#size-cells = <0>;
474
+			power-domains = <&zynqmp_firmware PD_ETH_2>;
389
475
 		};
390
476
 
391
477
 		gem3: ethernet@ff0e0000 {
..
..
@@ -397,17 +483,20 @@
397
483
 			clock-names = "pclk", "hclk", "tx_clk";
398
484
 			#address-cells = <1>;
399
485
 			#size-cells = <0>;
486
+			power-domains = <&zynqmp_firmware PD_ETH_3>;
400
487
 		};
401
488
 
402
489
 		gpio: gpio@ff0a0000 {
403
490
 			compatible = "xlnx,zynqmp-gpio-1.0";
404
491
 			status = "disabled";
405
492
 			#gpio-cells = <0x2>;
493
+			gpio-controller;
406
494
 			interrupt-parent = <&gic>;
407
495
 			interrupts = <0 16 4>;
408
496
 			interrupt-controller;
409
497
 			#interrupt-cells = <2>;
410
498
 			reg = <0x0 0xff0a0000 0x0 0x1000>;
499
+			power-domains = <&zynqmp_firmware PD_GPIO>;
411
500
 		};
412
501
 
413
502
 		i2c0: i2c@ff020000 {
..
..
@@ -418,6 +507,7 @@
418
507
 			reg = <0x0 0xff020000 0x0 0x1000>;
419
508
 			#address-cells = <1>;
420
509
 			#size-cells = <0>;
510
+			power-domains = <&zynqmp_firmware PD_I2C_0>;
421
511
 		};
422
512
 
423
513
 		i2c1: i2c@ff030000 {
..
..
@@ -428,6 +518,7 @@
428
518
 			reg = <0x0 0xff030000 0x0 0x1000>;
429
519
 			#address-cells = <1>;
430
520
 			#size-cells = <0>;
521
+			power-domains = <&zynqmp_firmware PD_I2C_1>;
431
522
 		};
432
523
 
433
524
 		pcie: pcie@fd0e0000 {
..
..
@@ -459,11 +550,21 @@
459
550
 					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
460
551
 					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
461
552
 					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
553
+			power-domains = <&zynqmp_firmware PD_PCIE>;
462
554
 			pcie_intc: legacy-interrupt-controller {
463
555
 				interrupt-controller;
464
556
 				#address-cells = <0>;
465
557
 				#interrupt-cells = <1>;
466
558
 			};
559
+		};
560
+
561
+		psgtr: phy@fd400000 {
562
+			compatible = "xlnx,zynqmp-psgtr-v1.1";
563
+			status = "disabled";
564
+			reg = <0x0 0xfd400000 0x0 0x40000>,
565
+			      <0x0 0xfd3d0000 0x0 0x1000>;
566
+			reg-names = "serdes", "siou";
567
+			#phy-cells = <4>;
467
568
 		};
468
569
 
469
570
 		rtc: rtc@ffa60000 {
..
..
@@ -482,27 +583,34 @@
482
583
 			reg = <0x0 0xfd0c0000 0x0 0x2000>;
483
584
 			interrupt-parent = <&gic>;
484
585
 			interrupts = <0 133 4>;
586
+			power-domains = <&zynqmp_firmware PD_SATA>;
485
587
 		};
486
588
 
487
-		sdhci0: sdhci@ff160000 {
488
-			compatible = "arasan,sdhci-8.9a";
589
+		sdhci0: mmc@ff160000 {
590
+			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
489
591
 			status = "disabled";
490
592
 			interrupt-parent = <&gic>;
491
593
 			interrupts = <0 48 4>;
492
594
 			reg = <0x0 0xff160000 0x0 0x1000>;
493
595
 			clock-names = "clk_xin", "clk_ahb";
596
+			#clock-cells = <1>;
597
+			clock-output-names = "clk_out_sd0", "clk_in_sd0";
598
+			power-domains = <&zynqmp_firmware PD_SD_0>;
494
599
 		};
495
600
 
496
-		sdhci1: sdhci@ff170000 {
497
-			compatible = "arasan,sdhci-8.9a";
601
+		sdhci1: mmc@ff170000 {
602
+			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
498
603
 			status = "disabled";
499
604
 			interrupt-parent = <&gic>;
500
605
 			interrupts = <0 49 4>;
501
606
 			reg = <0x0 0xff170000 0x0 0x1000>;
502
607
 			clock-names = "clk_xin", "clk_ahb";
608
+			#clock-cells = <1>;
609
+			clock-output-names = "clk_out_sd1", "clk_in_sd1";
610
+			power-domains = <&zynqmp_firmware PD_SD_1>;
503
611
 		};
504
612
 
505
-		smmu: smmu@fd800000 {
613
+		smmu: iommu@fd800000 {
506
614
 			compatible = "arm,mmu-500";
507
615
 			reg = <0x0 0xfd800000 0x0 0x20000>;
508
616
 			status = "disabled";
..
..
@@ -524,6 +632,7 @@
524
632
 			clock-names = "ref_clk", "pclk";
525
633
 			#address-cells = <1>;
526
634
 			#size-cells = <0>;
635
+			power-domains = <&zynqmp_firmware PD_SPI_0>;
527
636
 		};
528
637
 
529
638
 		spi1: spi@ff050000 {
..
..
@@ -535,6 +644,7 @@
535
644
 			clock-names = "ref_clk", "pclk";
536
645
 			#address-cells = <1>;
537
646
 			#size-cells = <0>;
647
+			power-domains = <&zynqmp_firmware PD_SPI_1>;
538
648
 		};
539
649
 
540
650
 		ttc0: timer@ff110000 {
..
..
@@ -544,6 +654,7 @@
544
654
 			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
545
655
 			reg = <0x0 0xff110000 0x0 0x1000>;
546
656
 			timer-width = <32>;
657
+			power-domains = <&zynqmp_firmware PD_TTC_0>;
547
658
 		};
548
659
 
549
660
 		ttc1: timer@ff120000 {
..
..
@@ -553,6 +664,7 @@
553
664
 			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
554
665
 			reg = <0x0 0xff120000 0x0 0x1000>;
555
666
 			timer-width = <32>;
667
+			power-domains = <&zynqmp_firmware PD_TTC_1>;
556
668
 		};
557
669
 
558
670
 		ttc2: timer@ff130000 {
..
..
@@ -562,6 +674,7 @@
562
674
 			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
563
675
 			reg = <0x0 0xff130000 0x0 0x1000>;
564
676
 			timer-width = <32>;
677
+			power-domains = <&zynqmp_firmware PD_TTC_2>;
565
678
 		};
566
679
 
567
680
 		ttc3: timer@ff140000 {
..
..
@@ -571,6 +684,7 @@
571
684
 			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
572
685
 			reg = <0x0 0xff140000 0x0 0x1000>;
573
686
 			timer-width = <32>;
687
+			power-domains = <&zynqmp_firmware PD_TTC_3>;
574
688
 		};
575
689
 
576
690
 		uart0: serial@ff000000 {
..
..
@@ -580,6 +694,7 @@
580
694
 			interrupts = <0 21 4>;
581
695
 			reg = <0x0 0xff000000 0x0 0x1000>;
582
696
 			clock-names = "uart_clk", "pclk";
697
+			power-domains = <&zynqmp_firmware PD_UART_0>;
583
698
 		};
584
699
 
585
700
 		uart1: serial@ff010000 {
..
..
@@ -589,6 +704,7 @@
589
704
 			interrupts = <0 22 4>;
590
705
 			reg = <0x0 0xff010000 0x0 0x1000>;
591
706
 			clock-names = "uart_clk", "pclk";
707
+			power-domains = <&zynqmp_firmware PD_UART_1>;
592
708
 		};
593
709
 
594
710
 		usb0: usb@fe200000 {
..
..
@@ -598,6 +714,7 @@
598
714
 			interrupts = <0 65 4>;
599
715
 			reg = <0x0 0xfe200000 0x0 0x40000>;
600
716
 			clock-names = "clk_xin", "clk_ahb";
717
+			power-domains = <&zynqmp_firmware PD_USB_0>;
601
718
 		};
602
719
 
603
720
 		usb1: usb@fe300000 {
..
..
@@ -607,6 +724,7 @@
607
724
 			interrupts = <0 70 4>;
608
725
 			reg = <0x0 0xfe300000 0x0 0x40000>;
609
726
 			clock-names = "clk_xin", "clk_ahb";
727
+			power-domains = <&zynqmp_firmware PD_USB_1>;
610
728
 		};
611
729
 
612
730
 		watchdog0: watchdog@fd4d0000 {