| .. | .. |
|---|
| 2 | 2 | /* |
|---|
| 3 | 3 | * dts file for Xilinx ZynqMP ZCU104 |
|---|
| 4 | 4 | * |
|---|
| 5 | | - * (C) Copyright 2017 - 2018, Xilinx, Inc. |
|---|
| 5 | + * (C) Copyright 2017 - 2019, Xilinx, Inc. |
|---|
| 6 | 6 | * |
|---|
| 7 | 7 | * Michal Simek <michal.simek@xilinx.com> |
|---|
| 8 | 8 | */ |
|---|
| .. | .. |
|---|
| 10 | 10 | /dts-v1/; |
|---|
| 11 | 11 | |
|---|
| 12 | 12 | #include "zynqmp.dtsi" |
|---|
| 13 | | -#include "zynqmp-clk.dtsi" |
|---|
| 13 | +#include "zynqmp-clk-ccf.dtsi" |
|---|
| 14 | 14 | #include <dt-bindings/gpio/gpio.h> |
|---|
| 15 | 15 | |
|---|
| 16 | 16 | / { |
|---|
| .. | .. |
|---|
| 50 | 50 | status = "okay"; |
|---|
| 51 | 51 | phy-handle = <&phy0>; |
|---|
| 52 | 52 | phy-mode = "rgmii-id"; |
|---|
| 53 | | - phy0: phy@c { |
|---|
| 53 | + phy0: ethernet-phy@c { |
|---|
| 54 | 54 | reg = <0xc>; |
|---|
| 55 | 55 | ti,rx-internal-delay = <0x8>; |
|---|
| 56 | 56 | ti,tx-internal-delay = <0xa>; |
|---|
| 57 | 57 | ti,fifo-depth = <0x1>; |
|---|
| 58 | + ti,dp83867-rxctrl-strap-quirk; |
|---|
| 58 | 59 | }; |
|---|
| 59 | 60 | }; |
|---|
| 60 | 61 | |
|---|
| .. | .. |
|---|
| 117 | 118 | #address-cells = <1>; |
|---|
| 118 | 119 | #size-cells = <0>; |
|---|
| 119 | 120 | reg = <4>; |
|---|
| 120 | | - tca6416_u97: gpio@21 { |
|---|
| 121 | + tca6416_u97: gpio@20 { |
|---|
| 121 | 122 | compatible = "ti,tca6416"; |
|---|
| 122 | | - reg = <0x21>; |
|---|
| 123 | + reg = <0x20>; |
|---|
| 123 | 124 | gpio-controller; |
|---|
| 124 | 125 | #gpio-cells = <2>; |
|---|
| 125 | 126 | /* |
|---|
| .. | .. |
|---|
| 188 | 189 | /* ULPI SMSC USB3320 */ |
|---|
| 189 | 190 | &usb0 { |
|---|
| 190 | 191 | status = "okay"; |
|---|
| 192 | + dr_mode = "host"; |
|---|
| 191 | 193 | }; |
|---|
| 192 | 194 | |
|---|
| 193 | 195 | &watchdog0 { |
|---|