kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
..
..
@@ -2,7 +2,7 @@
2
2
 /*
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3
  * dts file for Xilinx ZynqMP ZCU102 RevA
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4
  *
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- * (C) Copyright 2015 - 2018, Xilinx, Inc.
5
+ * (C) Copyright 2015 - 2019, Xilinx, Inc.
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  *
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7
  * Michal Simek <michal.simek@xilinx.com>
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8
  */
..
..
@@ -10,7 +10,7 @@
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 /dts-v1/;
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11
 
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12
 #include "zynqmp.dtsi"
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-#include "zynqmp-clk.dtsi"
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+#include "zynqmp-clk-ccf.dtsi"
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 #include <dt-bindings/input/input.h>
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 #include <dt-bindings/gpio/gpio.h>
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16
 
..
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@@ -46,7 +46,7 @@
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 			label = "sw19";
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 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
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 			linux,code = <KEY_DOWN>;
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-			gpio-key,wakeup;
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+			wakeup-source;
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 			autorepeat;
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 		};
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52
 	};
..
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@@ -58,6 +58,79 @@
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 			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
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 			linux,default-trigger = "heartbeat";
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 		};
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+	};
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+
63
+	ina226-u76 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
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+	};
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+	ina226-u77 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
70
+	};
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+	ina226-u78 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
74
+	};
75
+	ina226-u87 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
78
+	};
79
+	ina226-u85 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
82
+	};
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+	ina226-u86 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
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+	};
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+	ina226-u93 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
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+	};
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+	ina226-u88 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
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+	};
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+	ina226-u15 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
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+	};
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+	ina226-u92 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
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+	};
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+	ina226-u79 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
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+	};
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+	ina226-u81 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
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+	};
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+	ina226-u80 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
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+	};
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+	ina226-u84 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
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+	};
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+	ina226-u16 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
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+	};
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+	ina226-u65 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
126
+	};
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+	ina226-u74 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
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+	};
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+	ina226-u75 {
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+		compatible = "iio-hwmon";
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+		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
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134
 	};
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 };
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136
 
..
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@@ -105,11 +178,12 @@
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 	status = "okay";
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 	phy-handle = <&phy0>;
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 	phy-mode = "rgmii-id";
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-	phy0: phy@21 {
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+	phy0: ethernet-phy@21 {
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 		reg = <21>;
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 		ti,rx-internal-delay = <0x8>;
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 		ti,tx-internal-delay = <0xa>;
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 		ti,fifo-depth = <0x1>;
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+		ti,dp83867-rxctrl-strap-quirk;
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 	};
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 };
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..
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@@ -124,40 +198,30 @@
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 	tca6416_u97: gpio@20 {
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 		compatible = "ti,tca6416";
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 		reg = <0x20>;
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-		gpio-controller;
201
+		gpio-controller; /* IRQ not connected */
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 		#gpio-cells = <2>;
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-		/*
130
-		 * IRQ not connected
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-		 * Lines:
132
-		 * 0 - PS_GTR_LAN_SEL0
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-		 * 1 - PS_GTR_LAN_SEL1
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-		 * 2 - PS_GTR_LAN_SEL2
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-		 * 3 - PS_GTR_LAN_SEL3
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-		 * 4 - PCI_CLK_DIR_SEL
137
-		 * 5 - IIC_MUX_RESET_B
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-		 * 6 - GEM3_EXP_RESET_B
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-		 * 7, 10 - 17 - not connected
140
-		 */
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-
142
-		gtr-sel0 {
203
+		gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
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+				"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
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+				"", "", "", "", "", "", "", "", "";
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+		gtr-sel0-hog {
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 			gpio-hog;
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 			gpios = <0 0>;
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 			output-low; /* PCIE = 0, DP = 1 */
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 			line-name = "sel0";
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 		};
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-		gtr-sel1 {
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+		gtr-sel1-hog {
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 			gpio-hog;
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 			gpios = <1 0>;
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 			output-high; /* PCIE = 0, DP = 1 */
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 			line-name = "sel1";
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 		};
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-		gtr-sel2 {
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+		gtr-sel2-hog {
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 			gpio-hog;
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 			gpios = <2 0>;
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 			output-high; /* PCIE = 0, USB0 = 1 */
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 			line-name = "sel2";
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 		};
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-		gtr-sel3 {
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+		gtr-sel3-hog {
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 			gpio-hog;
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 			gpios = <3 0>;
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 			output-high; /* PCIE = 0, SATA = 1 */
..
..
@@ -168,27 +232,12 @@
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 	tca6416_u61: gpio@21 {
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 		compatible = "ti,tca6416";
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 		reg = <0x21>;
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-		gpio-controller;
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+		gpio-controller; /* IRQ not connected */
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 		#gpio-cells = <2>;
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-		/*
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-		 * IRQ not connected
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-		 * Lines:
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-		 * 0 - VCCPSPLL_EN
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-		 * 1 - MGTRAVCC_EN
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-		 * 2 - MGTRAVTT_EN
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-		 * 3 - VCCPSDDRPLL_EN
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-		 * 4 - MIO26_PMU_INPUT_LS
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-		 * 5 - PL_PMBUS_ALERT
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-		 * 6 - PS_PMBUS_ALERT
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-		 * 7 - MAXIM_PMBUS_ALERT
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-		 * 10 - PL_DDR4_VTERM_EN
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-		 * 11 - PL_DDR4_VPP_2V5_EN
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-		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
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-		 * 13 - PS_DIMM_SUSPEND_EN
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-		 * 14 - PS_DDR4_VTERM_EN
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-		 * 15 - PS_DDR4_VPP_2V5_EN
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-		 * 16 - 17 - not connected
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-		 */
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+		gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
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+				"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
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+				"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
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+				"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
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 	};
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242
 
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 	i2c-mux@75 { /* u60 */
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@@ -201,53 +250,73 @@
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 			#size-cells = <0>;
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 			reg = <0>;
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 			/* PS_PMBUS */
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-			ina226@40 { /* u76 */
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+			u76: ina226@40 { /* u76 */
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 				compatible = "ti,ina226";
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+				#io-channel-cells = <1>;
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+				label = "ina226-u76";
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 				reg = <0x40>;
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 				shunt-resistor = <5000>;
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 			};
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-			ina226@41 { /* u77 */
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+			u77: ina226@41 { /* u77 */
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 				compatible = "ti,ina226";
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+				#io-channel-cells = <1>;
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+				label = "ina226-u77";
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 				reg = <0x41>;
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 				shunt-resistor = <5000>;
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 			};
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-			ina226@42 { /* u78 */
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+			u78: ina226@42 { /* u78 */
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 				compatible = "ti,ina226";
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+				#io-channel-cells = <1>;
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+				label = "ina226-u78";
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 				reg = <0x42>;
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 				shunt-resistor = <5000>;
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 			};
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-			ina226@43 { /* u87 */
274
+			u87: ina226@43 { /* u87 */
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 				compatible = "ti,ina226";
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+				#io-channel-cells = <1>;
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+				label = "ina226-u87";
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 				reg = <0x43>;
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 				shunt-resistor = <5000>;
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 			};
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-			ina226@44 { /* u85 */
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+			u85: ina226@44 { /* u85 */
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 				compatible = "ti,ina226";
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+				#io-channel-cells = <1>;
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+				label = "ina226-u85";
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 				reg = <0x44>;
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 				shunt-resistor = <5000>;
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 			};
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-			ina226@45 { /* u86 */
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+			u86: ina226@45 { /* u86 */
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 				compatible = "ti,ina226";
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+				#io-channel-cells = <1>;
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+				label = "ina226-u86";
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 				reg = <0x45>;
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 				shunt-resistor = <5000>;
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 			};
234
-			ina226@46 { /* u93 */
295
+			u93: ina226@46 { /* u93 */
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 				compatible = "ti,ina226";
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+				#io-channel-cells = <1>;
298
+				label = "ina226-u93";
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 				reg = <0x46>;
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 				shunt-resistor = <5000>;
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 			};
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-			ina226@47 { /* u88 */
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+			u88: ina226@47 { /* u88 */
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 				compatible = "ti,ina226";
304
+				#io-channel-cells = <1>;
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+				label = "ina226-u88";
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 				reg = <0x47>;
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 				shunt-resistor = <5000>;
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 			};
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-			ina226@4a { /* u15 */
309
+			u15: ina226@4a { /* u15 */
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 				compatible = "ti,ina226";
311
+				#io-channel-cells = <1>;
312
+				label = "ina226-u15";
246
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 				reg = <0x4a>;
247
314
 				shunt-resistor = <5000>;
248
315
 			};
249
-			ina226@4b { /* u92 */
316
+			u92: ina226@4b { /* u92 */
250
317
 				compatible = "ti,ina226";
318
+				#io-channel-cells = <1>;
319
+				label = "ina226-u92";
251
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 				reg = <0x4b>;
252
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 				shunt-resistor = <5000>;
253
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 			};
..
..
@@ -257,43 +326,59 @@
257
326
 			#size-cells = <0>;
258
327
 			reg = <1>;
259
328
 			/* PL_PMBUS */
260
-			ina226@40 { /* u79 */
329
+			u79: ina226@40 { /* u79 */
261
330
 				compatible = "ti,ina226";
331
+				#io-channel-cells = <1>;
332
+				label = "ina226-u79";
262
333
 				reg = <0x40>;
263
334
 				shunt-resistor = <2000>;
264
335
 			};
265
-			ina226@41 { /* u81 */
336
+			u81: ina226@41 { /* u81 */
266
337
 				compatible = "ti,ina226";
338
+				#io-channel-cells = <1>;
339
+				label = "ina226-u81";
267
340
 				reg = <0x41>;
268
341
 				shunt-resistor = <5000>;
269
342
 			};
270
-			ina226@42 { /* u80 */
343
+			u80: ina226@42 { /* u80 */
271
344
 				compatible = "ti,ina226";
345
+				#io-channel-cells = <1>;
346
+				label = "ina226-u80";
272
347
 				reg = <0x42>;
273
348
 				shunt-resistor = <5000>;
274
349
 			};
275
-			ina226@43 { /* u84 */
350
+			u84: ina226@43 { /* u84 */
276
351
 				compatible = "ti,ina226";
352
+				#io-channel-cells = <1>;
353
+				label = "ina226-u84";
277
354
 				reg = <0x43>;
278
355
 				shunt-resistor = <5000>;
279
356
 			};
280
-			ina226@44 { /* u16 */
357
+			u16: ina226@44 { /* u16 */
281
358
 				compatible = "ti,ina226";
359
+				#io-channel-cells = <1>;
360
+				label = "ina226-u16";
282
361
 				reg = <0x44>;
283
362
 				shunt-resistor = <5000>;
284
363
 			};
285
-			ina226@45 { /* u65 */
364
+			u65: ina226@45 { /* u65 */
286
365
 				compatible = "ti,ina226";
366
+				#io-channel-cells = <1>;
367
+				label = "ina226-u65";
287
368
 				reg = <0x45>;
288
369
 				shunt-resistor = <5000>;
289
370
 			};
290
-			ina226@46 { /* u74 */
371
+			u74: ina226@46 { /* u74 */
291
372
 				compatible = "ti,ina226";
373
+				#io-channel-cells = <1>;
374
+				label = "ina226-u74";
292
375
 				reg = <0x46>;
293
376
 				shunt-resistor = <5000>;
294
377
 			};
295
-			ina226@47 { /* u75 */
378
+			u75: ina226@47 { /* u75 */
296
379
 				compatible = "ti,ina226";
380
+				#io-channel-cells = <1>;
381
+				label = "ina226-u75";
297
382
 				reg = <0x47>;
298
383
 				shunt-resistor = <5000>;
299
384
 			};
..
..
@@ -413,6 +498,7 @@
413
498
 				temperature-stability = <50>;
414
499
 				factory-fout = <300000000>;
415
500
 				clock-frequency = <300000000>;
501
+				clock-output-names = "si570_user";
416
502
 			};
417
503
 		};
418
504
 		i2c@3 {
..
..
@@ -426,6 +512,7 @@
426
512
 				temperature-stability = <50>; /* copy from zc702 */
427
513
 				factory-fout = <156250000>;
428
514
 				clock-frequency = <148500000>;
515
+				clock-output-names = "si570_mgt";
429
516
 			};
430
517
 		};
431
518
 		i2c@4 {
..
..
@@ -539,6 +626,7 @@
539
626
 /* ULPI SMSC USB3320 */
540
627
 &usb0 {
541
628
 	status = "okay";
629
+	dr_mode = "host";
542
630
 };
543
631
 
544
632
 &watchdog0 {