| .. | .. |
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| 2 | 2 | /* |
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| 3 | 3 | * Device Tree Source for AM6 SoC Family |
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| 4 | 4 | * |
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| 5 | | - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ |
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| 5 | + * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ |
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| 6 | 6 | */ |
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| 7 | 7 | |
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| 8 | 8 | #include <dt-bindings/gpio/gpio.h> |
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| 9 | 9 | #include <dt-bindings/interrupt-controller/irq.h> |
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| 10 | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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| 11 | +#include <dt-bindings/pinctrl/k3.h> |
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| 12 | +#include <dt-bindings/soc/ti,sci_pm_domain.h> |
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| 11 | 13 | |
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| 12 | 14 | / { |
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| 13 | 15 | model = "Texas Instruments K3 AM654 SoC"; |
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| .. | .. |
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| 15 | 17 | interrupt-parent = <&gic500>; |
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| 16 | 18 | #address-cells = <2>; |
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| 17 | 19 | #size-cells = <2>; |
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| 20 | + |
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| 21 | + aliases { |
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| 22 | + serial0 = &wkup_uart0; |
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| 23 | + serial1 = &mcu_uart0; |
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| 24 | + serial2 = &main_uart0; |
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| 25 | + serial3 = &main_uart1; |
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| 26 | + serial4 = &main_uart2; |
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| 27 | + i2c0 = &wkup_i2c0; |
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| 28 | + i2c1 = &mcu_i2c0; |
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| 29 | + i2c2 = &main_i2c0; |
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| 30 | + i2c3 = &main_i2c1; |
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| 31 | + i2c4 = &main_i2c2; |
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| 32 | + i2c5 = &main_i2c3; |
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| 33 | + ethernet0 = &cpsw_port1; |
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| 34 | + }; |
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| 18 | 35 | |
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| 19 | 36 | chosen { }; |
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| 20 | 37 | |
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| .. | .. |
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| 44 | 61 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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| 45 | 62 | }; |
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| 46 | 63 | |
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| 47 | | - cbass_main: interconnect@100000 { |
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| 64 | + cbass_main: bus@100000 { |
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| 48 | 65 | compatible = "simple-bus"; |
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| 49 | 66 | #address-cells = <2>; |
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| 50 | 67 | #size-cells = <2>; |
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| .. | .. |
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| 53 | 70 | <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ |
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| 54 | 71 | <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ |
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| 55 | 72 | <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ |
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| 73 | + <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ |
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| 74 | + <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ |
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| 56 | 75 | /* MCUSS Range */ |
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| 57 | 76 | <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, |
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| 58 | 77 | <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, |
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| 78 | + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ |
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| 79 | + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, |
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| 80 | + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, |
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| 81 | + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, |
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| 59 | 82 | <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, |
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| 60 | 83 | <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, |
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| 61 | 84 | <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, |
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| 62 | | - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; |
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| 85 | + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, |
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| 86 | + <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, |
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| 87 | + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */ |
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| 88 | + <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>, |
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| 89 | + <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, |
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| 90 | + <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; |
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| 63 | 91 | |
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| 64 | | - cbass_mcu: interconnect@28380000 { |
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| 92 | + cbass_mcu: bus@28380000 { |
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| 65 | 93 | compatible = "simple-bus"; |
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| 66 | 94 | #address-cells = <2>; |
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| 67 | 95 | #size-cells = <2>; |
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| 68 | 96 | ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ |
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| 69 | 97 | <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ |
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| 98 | + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ |
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| 99 | + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ |
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| 100 | + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ |
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| 101 | + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */ |
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| 70 | 102 | <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ |
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| 71 | 103 | <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ |
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| 72 | 104 | <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ |
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| 73 | | - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */ |
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| 105 | + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */ |
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| 106 | + <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */ |
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| 107 | + <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ |
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| 108 | + <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ |
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| 74 | 109 | |
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| 75 | | - cbass_wakeup: interconnect@42040000 { |
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| 110 | + cbass_wakeup: bus@42040000 { |
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| 76 | 111 | compatible = "simple-bus"; |
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| 77 | 112 | #address-cells = <1>; |
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| 78 | 113 | #size-cells = <1>; |
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| .. | .. |
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| 85 | 120 | |
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| 86 | 121 | /* Now include the peripherals for each bus segments */ |
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| 87 | 122 | #include "k3-am65-main.dtsi" |
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| 123 | +#include "k3-am65-mcu.dtsi" |
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| 124 | +#include "k3-am65-wakeup.dtsi" |
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