kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
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@@ -8,8 +8,6 @@
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 #include <dt-bindings/gpio/gpio.h>
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 #include <dt-bindings/gpio/uniphier-gpio.h>
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-/memreserve/ 0x80000000 0x02000000;
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-
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 / {
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 	compatible = "socionext,uniphier-ld11";
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 	#address-cells = <2>;
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@@ -33,7 +31,7 @@
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 		cpu0: cpu@0 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			reg = <0 0x000>;
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 			clocks = <&sys_clk 33>;
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 			enable-method = "psci";
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@@ -42,7 +40,7 @@
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 		cpu1: cpu@1 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			reg = <0 0x001>;
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 			clocks = <&sys_clk 33>;
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 			enable-method = "psci";
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@@ -110,11 +108,48 @@
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 			     <1 10 4>;
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 	};
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+	reserved-memory {
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+		#address-cells = <2>;
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+		#size-cells = <2>;
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+		ranges;
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+
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+		secure-memory@81000000 {
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+			reg = <0x0 0x81000000 0x0 0x01000000>;
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+			no-map;
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+		};
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+	};
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+
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 	soc@0 {
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 		compatible = "simple-bus";
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0 0 0xffffffff>;
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+
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+		spi0: spi@54006000 {
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+			compatible = "socionext,uniphier-scssi";
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+			status = "disabled";
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+			reg = <0x54006000 0x100>;
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+			interrupts = <0 39 4>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&pinctrl_spi0>;
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+			clocks = <&peri_clk 11>;
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+			resets = <&peri_rst 11>;
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+		};
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+
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+		spi1: spi@54006100 {
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+			compatible = "socionext,uniphier-scssi";
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+			status = "disabled";
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+			reg = <0x54006100 0x100>;
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+			interrupts = <0 216 4>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&pinctrl_spi1>;
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+			clocks = <&peri_clk 12>;
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+			resets = <&peri_rst 12>;
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+		};
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 		serial0: serial@54006800 {
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 			compatible = "socionext,uniphier-uart";
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@@ -402,7 +437,7 @@
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 			};
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 		};
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-		emmc: sdhc@5a000000 {
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+		emmc: mmc@5a000000 {
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 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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 			reg = <0x5a000000 0x400>;
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 			interrupts = <0 78 4>;
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@@ -432,6 +467,8 @@
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 				 <&mio_clk 12>;
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 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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 				 <&mio_rst 12>;
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+			phy-names = "usb";
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+			phys = <&usb_phy0>;
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 			has-transaction-translator;
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 		};
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@@ -446,6 +483,8 @@
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 				 <&mio_clk 13>;
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 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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 				 <&mio_rst 13>;
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+			phy-names = "usb";
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+			phys = <&usb_phy1>;
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 			has-transaction-translator;
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 		};
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..
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@@ -460,6 +499,8 @@
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 				 <&mio_clk 14>;
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 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
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 				 <&mio_rst 14>;
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+			phy-names = "usb";
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+			phys = <&usb_phy2>;
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 			has-transaction-translator;
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 		};
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@@ -488,6 +529,27 @@
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 			pinctrl: pinctrl {
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 				compatible = "socionext,uniphier-ld11-pinctrl";
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 			};
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+
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+			usb-phy {
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+				compatible = "socionext,uniphier-ld11-usb2-phy";
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
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+				usb_phy0: phy@0 {
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+					reg = <0>;
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+					#phy-cells = <0>;
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+				};
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+
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+				usb_phy1: phy@1 {
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+					reg = <1>;
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+					#phy-cells = <0>;
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+				};
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+
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+				usb_phy2: phy@2 {
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+					reg = <2>;
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+					#phy-cells = <0>;
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+				};
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+			};
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 		};
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 		soc-glue@5f900000 {
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@@ -508,7 +570,15 @@
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 			};
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 		};
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-		aidet: aidet@5fc20000 {
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+		xdmac: dma-controller@5fc10000 {
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+			compatible = "socionext,uniphier-xdmac";
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+			reg = <0x5fc10000 0x5300>;
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+			interrupts = <0 188 4>;
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+			dma-channels = <16>;
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+			#dma-cells = <2>;
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+		};
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+
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+		aidet: interrupt-controller@5fc20000 {
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 			compatible = "socionext,uniphier-ld11-aidet";
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 			reg = <0x5fc20000 0x200>;
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 			interrupt-controller;
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@@ -563,16 +633,20 @@
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 			};
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 		};
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-		nand: nand@68000000 {
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+		nand: nand-controller@68000000 {
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 			compatible = "socionext,uniphier-denali-nand-v5b";
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 			status = "disabled";
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 			reg-names = "nand_data", "denali_reg";
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 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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 			interrupts = <0 65 4>;
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 			pinctrl-names = "default";
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 			pinctrl-0 = <&pinctrl_nand>;
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-			clocks = <&sys_clk 2>;
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-			resets = <&sys_rst 2>;
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+			clock-names = "nand", "nand_x", "ecc";
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+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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+			reset-names = "nand", "reg";
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+			resets = <&sys_rst 2>, <&sys_rst 2>;
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 		};
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 	};
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 };