~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,11 +1,11 @@
1		-/* SPDX-License-Identifier: GPL-2.0 */
	1	+// SPDX-License-Identifier: GPL-2.0
2	2	/*
3		- * Device Tree Source for the r8a77990 SoC
	3	+ * Device Tree Source for the R-Car E3 (R8A77990) SoC
4	4	*
5		- * Copyright (C) 2018 Renesas Electronics Corp.
	5	+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
6	6	*/
7	7
8		-#include <dt-bindings/clock/renesas-cpg-mssr.h>
	8	+#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
10	10	#include <dt-bindings/power/r8a77990-sysc.h>
11	11
..	..	@@ -14,33 +14,116 @@
14	14	#address-cells = <2>;
15	15	#size-cells = <2>;
16	16
	17	+ aliases {
	18	+ i2c0 = &i2c0;
	19	+ i2c1 = &i2c1;
	20	+ i2c2 = &i2c2;
	21	+ i2c3 = &i2c3;
	22	+ i2c4 = &i2c4;
	23	+ i2c5 = &i2c5;
	24	+ i2c6 = &i2c6;
	25	+ i2c7 = &i2c7;
	26	+ };
	27	+
	28	+ /*
	29	+ * The external audio clocks are configured as 0 Hz fixed frequency
	30	+ * clocks by default.
	31	+ * Boards that provide audio clocks should override them.
	32	+ */
	33	+ audio_clk_a: audio_clk_a {
	34	+ compatible = "fixed-clock";
	35	+ #clock-cells = <0>;
	36	+ clock-frequency = <0>;
	37	+ };
	38	+
	39	+ audio_clk_b: audio_clk_b {
	40	+ compatible = "fixed-clock";
	41	+ #clock-cells = <0>;
	42	+ clock-frequency = <0>;
	43	+ };
	44	+
	45	+ audio_clk_c: audio_clk_c {
	46	+ compatible = "fixed-clock";
	47	+ #clock-cells = <0>;
	48	+ clock-frequency = <0>;
	49	+ };
	50	+
	51	+ /* External CAN clock - to be overridden by boards that provide it */
	52	+ can_clk: can {
	53	+ compatible = "fixed-clock";
	54	+ #clock-cells = <0>;
	55	+ clock-frequency = <0>;
	56	+ };
	57	+
	58	+ cluster1_opp: opp_table10 {
	59	+ compatible = "operating-points-v2";
	60	+ opp-shared;
	61	+ opp-800000000 {
	62	+ opp-hz = /bits/ 64 <800000000>;
	63	+ opp-microvolt = <820000>;
	64	+ clock-latency-ns = <300000>;
	65	+ };
	66	+ opp-1000000000 {
	67	+ opp-hz = /bits/ 64 <1000000000>;
	68	+ opp-microvolt = <820000>;
	69	+ clock-latency-ns = <300000>;
	70	+ };
	71	+ opp-1200000000 {
	72	+ opp-hz = /bits/ 64 <1200000000>;
	73	+ opp-microvolt = <820000>;
	74	+ clock-latency-ns = <300000>;
	75	+ opp-suspend;
	76	+ };
	77	+ };
	78	+
17	79	cpus {
18	80	#address-cells = <1>;
19	81	#size-cells = <0>;
20	82
21	83	a53_0: cpu@0 {
22		- compatible = "arm,cortex-a53", "arm,armv8";
	84	+ compatible = "arm,cortex-a53";
23	85	reg = <0>;
24	86	device_type = "cpu";
25		- power-domains = <&sysc 5>;
	87	+ #cooling-cells = <2>;
	88	+ power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
26	89	next-level-cache = <&L2_CA53>;
27	90	enable-method = "psci";
	91	+ cpu-idle-states = <&CPU_SLEEP_0>;
	92	+ dynamic-power-coefficient = <277>;
	93	+ clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
	94	+ operating-points-v2 = <&cluster1_opp>;
28	95	};
29	96
30	97	a53_1: cpu@1 {
31		- compatible = "arm,cortex-a53", "arm,armv8";
	98	+ compatible = "arm,cortex-a53";
32	99	reg = <1>;
33	100	device_type = "cpu";
34		- power-domains = <&sysc 6>;
	101	+ power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
35	102	next-level-cache = <&L2_CA53>;
36	103	enable-method = "psci";
	104	+ cpu-idle-states = <&CPU_SLEEP_0>;
	105	+ clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
	106	+ operating-points-v2 = <&cluster1_opp>;
37	107	};
38	108
39	109	L2_CA53: cache-controller-0 {
40	110	compatible = "cache";
41		- power-domains = <&sysc 21>;
	111	+ power-domains = <&sysc R8A77990_PD_CA53_SCU>;
42	112	cache-unified;
43	113	cache-level = <2>;
	114	+ };
	115	+
	116	+ idle-states {
	117	+ entry-method = "psci";
	118	+
	119	+ CPU_SLEEP_0: cpu-sleep-0 {
	120	+ compatible = "arm,idle-state";
	121	+ arm,psci-suspend-param = <0x0010000>;
	122	+ local-timer-stop;
	123	+ entry-latency-us = <700>;
	124	+ exit-latency-us = <700>;
	125	+ min-residency-us = <5000>;
	126	+ };
44	127	};
45	128	};
46	129
..	..	@@ -48,6 +131,13 @@
48	131	compatible = "fixed-clock";
49	132	#clock-cells = <0>;
50	133	/* This value must be overridden by the board */
	134	+ clock-frequency = <0>;
	135	+ };
	136	+
	137	+ /* External PCIe clock - can be overridden by the board */
	138	+ pcie_bus_clk: pcie_bus {
	139	+ compatible = "fixed-clock";
	140	+ #clock-cells = <0>;
51	141	clock-frequency = <0>;
52	142	};
53	143
..	..	@@ -63,6 +153,13 @@
63	153	method = "smc";
64	154	};
65	155
	156	+ /* External SCIF clock - to be overridden by boards that provide it */
	157	+ scif_clk: scif {
	158	+ compatible = "fixed-clock";
	159	+ #clock-cells = <0>;
	160	+ clock-frequency = <0>;
	161	+ };
	162	+
66	163	soc: soc {
67	164	compatible = "simple-bus";
68	165	interrupt-parent = <&gic>;
..	..	@@ -75,7 +172,7 @@
75	172	"renesas,rcar-gen3-wdt";
76	173	reg = <0 0xe6020000 0 0x0c>;
77	174	clocks = <&cpg CPG_MOD 402>;
78		- power-domains = <&sysc 32>;
	175	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
79	176	resets = <&cpg 402>;
80	177	status = "disabled";
81	178	};
..	..	@@ -91,7 +188,7 @@
91	188	#interrupt-cells = <2>;
92	189	interrupt-controller;
93	190	clocks = <&cpg CPG_MOD 912>;
94		- power-domains = <&sysc 32>;
	191	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
95	192	resets = <&cpg 912>;
96	193	};
97	194
..	..	@@ -106,7 +203,7 @@
106	203	#interrupt-cells = <2>;
107	204	interrupt-controller;
108	205	clocks = <&cpg CPG_MOD 911>;
109		- power-domains = <&sysc 32>;
	206	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
110	207	resets = <&cpg 911>;
111	208	};
112	209
..	..	@@ -121,7 +218,7 @@
121	218	#interrupt-cells = <2>;
122	219	interrupt-controller;
123	220	clocks = <&cpg CPG_MOD 910>;
124		- power-domains = <&sysc 32>;
	221	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
125	222	resets = <&cpg 910>;
126	223	};
127	224
..	..	@@ -136,7 +233,7 @@
136	233	#interrupt-cells = <2>;
137	234	interrupt-controller;
138	235	clocks = <&cpg CPG_MOD 909>;
139		- power-domains = <&sysc 32>;
	236	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
140	237	resets = <&cpg 909>;
141	238	};
142	239
..	..	@@ -151,7 +248,7 @@
151	248	#interrupt-cells = <2>;
152	249	interrupt-controller;
153	250	clocks = <&cpg CPG_MOD 908>;
154		- power-domains = <&sysc 32>;
	251	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
155	252	resets = <&cpg 908>;
156	253	};
157	254
..	..	@@ -166,7 +263,7 @@
166	263	#interrupt-cells = <2>;
167	264	interrupt-controller;
168	265	clocks = <&cpg CPG_MOD 907>;
169		- power-domains = <&sysc 32>;
	266	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
170	267	resets = <&cpg 907>;
171	268	};
172	269
..	..	@@ -181,13 +278,97 @@
181	278	#interrupt-cells = <2>;
182	279	interrupt-controller;
183	280	clocks = <&cpg CPG_MOD 906>;
184		- power-domains = <&sysc 32>;
	281	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
185	282	resets = <&cpg 906>;
186	283	};
187	284
188		- pfc: pin-controller@e6060000 {
	285	+ pfc: pinctrl@e6060000 {
189	286	compatible = "renesas,pfc-r8a77990";
190	287	reg = <0 0xe6060000 0 0x508>;
	288	+ };
	289	+
	290	+ i2c_dvfs: i2c@e60b0000 {
	291	+ #address-cells = <1>;
	292	+ #size-cells = <0>;
	293	+ compatible = "renesas,iic-r8a77990";
	294	+ reg = <0 0xe60b0000 0 0x15>;
	295	+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	296	+ clocks = <&cpg CPG_MOD 926>;
	297	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	298	+ resets = <&cpg 926>;
	299	+ dmas = <&dmac0 0x11>, <&dmac0 0x10>;
	300	+ dma-names = "tx", "rx";
	301	+ status = "disabled";
	302	+ };
	303	+
	304	+ cmt0: timer@e60f0000 {
	305	+ compatible = "renesas,r8a77990-cmt0",
	306	+ "renesas,rcar-gen3-cmt0";
	307	+ reg = <0 0xe60f0000 0 0x1004>;
	308	+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	309	+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	310	+ clocks = <&cpg CPG_MOD 303>;
	311	+ clock-names = "fck";
	312	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	313	+ resets = <&cpg 303>;
	314	+ status = "disabled";
	315	+ };
	316	+
	317	+ cmt1: timer@e6130000 {
	318	+ compatible = "renesas,r8a77990-cmt1",
	319	+ "renesas,rcar-gen3-cmt1";
	320	+ reg = <0 0xe6130000 0 0x1004>;
	321	+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	322	+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	323	+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
	324	+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	325	+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
	326	+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	327	+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
	328	+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	329	+ clocks = <&cpg CPG_MOD 302>;
	330	+ clock-names = "fck";
	331	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	332	+ resets = <&cpg 302>;
	333	+ status = "disabled";
	334	+ };
	335	+
	336	+ cmt2: timer@e6140000 {
	337	+ compatible = "renesas,r8a77990-cmt1",
	338	+ "renesas,rcar-gen3-cmt1";
	339	+ reg = <0 0xe6140000 0 0x1004>;
	340	+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
	341	+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
	342	+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
	343	+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
	344	+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
	345	+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
	346	+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
	347	+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	348	+ clocks = <&cpg CPG_MOD 301>;
	349	+ clock-names = "fck";
	350	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	351	+ resets = <&cpg 301>;
	352	+ status = "disabled";
	353	+ };
	354	+
	355	+ cmt3: timer@e6148000 {
	356	+ compatible = "renesas,r8a77990-cmt1",
	357	+ "renesas,rcar-gen3-cmt1";
	358	+ reg = <0 0xe6148000 0 0x1004>;
	359	+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
	360	+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
	361	+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
	362	+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
	363	+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
	364	+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
	365	+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
	366	+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	367	+ clocks = <&cpg CPG_MOD 300>;
	368	+ clock-names = "fck";
	369	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	370	+ resets = <&cpg 300>;
	371	+ status = "disabled";
191	372	};
192	373
193	374	cpg: clock-controller@e6150000 {
..	..	@@ -211,7 +392,432 @@
211	392	#power-domain-cells = <1>;
212	393	};
213	394
214		- ipmmu_ds0: mmu@e6740000 {
	395	+ thermal: thermal@e6190000 {
	396	+ compatible = "renesas,thermal-r8a77990";
	397	+ reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
	398	+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	399	+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	400	+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	401	+ clocks = <&cpg CPG_MOD 522>;
	402	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	403	+ resets = <&cpg 522>;
	404	+ #thermal-sensor-cells = <0>;
	405	+ };
	406	+
	407	+ intc_ex: interrupt-controller@e61c0000 {
	408	+ compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
	409	+ #interrupt-cells = <2>;
	410	+ interrupt-controller;
	411	+ reg = <0 0xe61c0000 0 0x200>;
	412	+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	413	+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	414	+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	415	+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	416	+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	417	+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	418	+ clocks = <&cpg CPG_MOD 407>;
	419	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	420	+ resets = <&cpg 407>;
	421	+ };
	422	+
	423	+ i2c0: i2c@e6500000 {
	424	+ #address-cells = <1>;
	425	+ #size-cells = <0>;
	426	+ compatible = "renesas,i2c-r8a77990",
	427	+ "renesas,rcar-gen3-i2c";
	428	+ reg = <0 0xe6500000 0 0x40>;
	429	+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	430	+ clocks = <&cpg CPG_MOD 931>;
	431	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	432	+ resets = <&cpg 931>;
	433	+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
	434	+ <&dmac2 0x91>, <&dmac2 0x90>;
	435	+ dma-names = "tx", "rx", "tx", "rx";
	436	+ i2c-scl-internal-delay-ns = <110>;
	437	+ status = "disabled";
	438	+ };
	439	+
	440	+ i2c1: i2c@e6508000 {
	441	+ #address-cells = <1>;
	442	+ #size-cells = <0>;
	443	+ compatible = "renesas,i2c-r8a77990",
	444	+ "renesas,rcar-gen3-i2c";
	445	+ reg = <0 0xe6508000 0 0x40>;
	446	+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	447	+ clocks = <&cpg CPG_MOD 930>;
	448	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	449	+ resets = <&cpg 930>;
	450	+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
	451	+ <&dmac2 0x93>, <&dmac2 0x92>;
	452	+ dma-names = "tx", "rx", "tx", "rx";
	453	+ i2c-scl-internal-delay-ns = <6>;
	454	+ status = "disabled";
	455	+ };
	456	+
	457	+ i2c2: i2c@e6510000 {
	458	+ #address-cells = <1>;
	459	+ #size-cells = <0>;
	460	+ compatible = "renesas,i2c-r8a77990",
	461	+ "renesas,rcar-gen3-i2c";
	462	+ reg = <0 0xe6510000 0 0x40>;
	463	+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	464	+ clocks = <&cpg CPG_MOD 929>;
	465	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	466	+ resets = <&cpg 929>;
	467	+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
	468	+ <&dmac2 0x95>, <&dmac2 0x94>;
	469	+ dma-names = "tx", "rx", "tx", "rx";
	470	+ i2c-scl-internal-delay-ns = <6>;
	471	+ status = "disabled";
	472	+ };
	473	+
	474	+ i2c3: i2c@e66d0000 {
	475	+ #address-cells = <1>;
	476	+ #size-cells = <0>;
	477	+ compatible = "renesas,i2c-r8a77990",
	478	+ "renesas,rcar-gen3-i2c";
	479	+ reg = <0 0xe66d0000 0 0x40>;
	480	+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	481	+ clocks = <&cpg CPG_MOD 928>;
	482	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	483	+ resets = <&cpg 928>;
	484	+ dmas = <&dmac0 0x97>, <&dmac0 0x96>;
	485	+ dma-names = "tx", "rx";
	486	+ i2c-scl-internal-delay-ns = <110>;
	487	+ status = "disabled";
	488	+ };
	489	+
	490	+ i2c4: i2c@e66d8000 {
	491	+ #address-cells = <1>;
	492	+ #size-cells = <0>;
	493	+ compatible = "renesas,i2c-r8a77990",
	494	+ "renesas,rcar-gen3-i2c";
	495	+ reg = <0 0xe66d8000 0 0x40>;
	496	+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	497	+ clocks = <&cpg CPG_MOD 927>;
	498	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	499	+ resets = <&cpg 927>;
	500	+ dmas = <&dmac0 0x99>, <&dmac0 0x98>;
	501	+ dma-names = "tx", "rx";
	502	+ i2c-scl-internal-delay-ns = <6>;
	503	+ status = "disabled";
	504	+ };
	505	+
	506	+ i2c5: i2c@e66e0000 {
	507	+ #address-cells = <1>;
	508	+ #size-cells = <0>;
	509	+ compatible = "renesas,i2c-r8a77990",
	510	+ "renesas,rcar-gen3-i2c";
	511	+ reg = <0 0xe66e0000 0 0x40>;
	512	+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	513	+ clocks = <&cpg CPG_MOD 919>;
	514	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	515	+ resets = <&cpg 919>;
	516	+ dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
	517	+ dma-names = "tx", "rx";
	518	+ i2c-scl-internal-delay-ns = <6>;
	519	+ status = "disabled";
	520	+ };
	521	+
	522	+ i2c6: i2c@e66e8000 {
	523	+ #address-cells = <1>;
	524	+ #size-cells = <0>;
	525	+ compatible = "renesas,i2c-r8a77990",
	526	+ "renesas,rcar-gen3-i2c";
	527	+ reg = <0 0xe66e8000 0 0x40>;
	528	+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	529	+ clocks = <&cpg CPG_MOD 918>;
	530	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	531	+ resets = <&cpg 918>;
	532	+ dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
	533	+ dma-names = "tx", "rx";
	534	+ i2c-scl-internal-delay-ns = <6>;
	535	+ status = "disabled";
	536	+ };
	537	+
	538	+ i2c7: i2c@e6690000 {
	539	+ #address-cells = <1>;
	540	+ #size-cells = <0>;
	541	+ compatible = "renesas,i2c-r8a77990",
	542	+ "renesas,rcar-gen3-i2c";
	543	+ reg = <0 0xe6690000 0 0x40>;
	544	+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	545	+ clocks = <&cpg CPG_MOD 1003>;
	546	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	547	+ resets = <&cpg 1003>;
	548	+ i2c-scl-internal-delay-ns = <6>;
	549	+ status = "disabled";
	550	+ };
	551	+
	552	+ hscif0: serial@e6540000 {
	553	+ compatible = "renesas,hscif-r8a77990",
	554	+ "renesas,rcar-gen3-hscif",
	555	+ "renesas,hscif";
	556	+ reg = <0 0xe6540000 0 0x60>;
	557	+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	558	+ clocks = <&cpg CPG_MOD 520>,
	559	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	560	+ <&scif_clk>;
	561	+ clock-names = "fck", "brg_int", "scif_clk";
	562	+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	563	+ <&dmac2 0x31>, <&dmac2 0x30>;
	564	+ dma-names = "tx", "rx", "tx", "rx";
	565	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	566	+ resets = <&cpg 520>;
	567	+ status = "disabled";
	568	+ };
	569	+
	570	+ hscif1: serial@e6550000 {
	571	+ compatible = "renesas,hscif-r8a77990",
	572	+ "renesas,rcar-gen3-hscif",
	573	+ "renesas,hscif";
	574	+ reg = <0 0xe6550000 0 0x60>;
	575	+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	576	+ clocks = <&cpg CPG_MOD 519>,
	577	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	578	+ <&scif_clk>;
	579	+ clock-names = "fck", "brg_int", "scif_clk";
	580	+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	581	+ <&dmac2 0x33>, <&dmac2 0x32>;
	582	+ dma-names = "tx", "rx", "tx", "rx";
	583	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	584	+ resets = <&cpg 519>;
	585	+ status = "disabled";
	586	+ };
	587	+
	588	+ hscif2: serial@e6560000 {
	589	+ compatible = "renesas,hscif-r8a77990",
	590	+ "renesas,rcar-gen3-hscif",
	591	+ "renesas,hscif";
	592	+ reg = <0 0xe6560000 0 0x60>;
	593	+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	594	+ clocks = <&cpg CPG_MOD 518>,
	595	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	596	+ <&scif_clk>;
	597	+ clock-names = "fck", "brg_int", "scif_clk";
	598	+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	599	+ <&dmac2 0x35>, <&dmac2 0x34>;
	600	+ dma-names = "tx", "rx", "tx", "rx";
	601	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	602	+ resets = <&cpg 518>;
	603	+ status = "disabled";
	604	+ };
	605	+
	606	+ hscif3: serial@e66a0000 {
	607	+ compatible = "renesas,hscif-r8a77990",
	608	+ "renesas,rcar-gen3-hscif",
	609	+ "renesas,hscif";
	610	+ reg = <0 0xe66a0000 0 0x60>;
	611	+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	612	+ clocks = <&cpg CPG_MOD 517>,
	613	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	614	+ <&scif_clk>;
	615	+ clock-names = "fck", "brg_int", "scif_clk";
	616	+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
	617	+ dma-names = "tx", "rx";
	618	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	619	+ resets = <&cpg 517>;
	620	+ status = "disabled";
	621	+ };
	622	+
	623	+ hscif4: serial@e66b0000 {
	624	+ compatible = "renesas,hscif-r8a77990",
	625	+ "renesas,rcar-gen3-hscif",
	626	+ "renesas,hscif";
	627	+ reg = <0 0xe66b0000 0 0x60>;
	628	+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	629	+ clocks = <&cpg CPG_MOD 516>,
	630	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	631	+ <&scif_clk>;
	632	+ clock-names = "fck", "brg_int", "scif_clk";
	633	+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
	634	+ dma-names = "tx", "rx";
	635	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	636	+ resets = <&cpg 516>;
	637	+ status = "disabled";
	638	+ };
	639	+
	640	+ hsusb: usb@e6590000 {
	641	+ compatible = "renesas,usbhs-r8a77990",
	642	+ "renesas,rcar-gen3-usbhs";
	643	+ reg = <0 0xe6590000 0 0x200>;
	644	+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	645	+ clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
	646	+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
	647	+ <&usb_dmac1 0>, <&usb_dmac1 1>;
	648	+ dma-names = "ch0", "ch1", "ch2", "ch3";
	649	+ renesas,buswait = <11>;
	650	+ phys = <&usb2_phy0 3>;
	651	+ phy-names = "usb";
	652	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	653	+ resets = <&cpg 704>, <&cpg 703>;
	654	+ status = "disabled";
	655	+ };
	656	+
	657	+ usb_dmac0: dma-controller@e65a0000 {
	658	+ compatible = "renesas,r8a77990-usb-dmac",
	659	+ "renesas,usb-dmac";
	660	+ reg = <0 0xe65a0000 0 0x100>;
	661	+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	662	+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	663	+ interrupt-names = "ch0", "ch1";
	664	+ clocks = <&cpg CPG_MOD 330>;
	665	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	666	+ resets = <&cpg 330>;
	667	+ #dma-cells = <1>;
	668	+ dma-channels = <2>;
	669	+ };
	670	+
	671	+ usb_dmac1: dma-controller@e65b0000 {
	672	+ compatible = "renesas,r8a77990-usb-dmac",
	673	+ "renesas,usb-dmac";
	674	+ reg = <0 0xe65b0000 0 0x100>;
	675	+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	676	+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	677	+ interrupt-names = "ch0", "ch1";
	678	+ clocks = <&cpg CPG_MOD 331>;
	679	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	680	+ resets = <&cpg 331>;
	681	+ #dma-cells = <1>;
	682	+ dma-channels = <2>;
	683	+ };
	684	+
	685	+ arm_cc630p: crypto@e6601000 {
	686	+ compatible = "arm,cryptocell-630p-ree";
	687	+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	688	+ reg = <0x0 0xe6601000 0 0x1000>;
	689	+ clocks = <&cpg CPG_MOD 229>;
	690	+ resets = <&cpg 229>;
	691	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	692	+ };
	693	+
	694	+ dmac0: dma-controller@e6700000 {
	695	+ compatible = "renesas,dmac-r8a77990",
	696	+ "renesas,rcar-dmac";
	697	+ reg = <0 0xe6700000 0 0x10000>;
	698	+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	699	+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	700	+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	701	+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	702	+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	703	+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	704	+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	705	+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	706	+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	707	+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	708	+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	709	+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	710	+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	711	+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	712	+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	713	+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	714	+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	715	+ interrupt-names = "error",
	716	+ "ch0", "ch1", "ch2", "ch3",
	717	+ "ch4", "ch5", "ch6", "ch7",
	718	+ "ch8", "ch9", "ch10", "ch11",
	719	+ "ch12", "ch13", "ch14", "ch15";
	720	+ clocks = <&cpg CPG_MOD 219>;
	721	+ clock-names = "fck";
	722	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	723	+ resets = <&cpg 219>;
	724	+ #dma-cells = <1>;
	725	+ dma-channels = <16>;
	726	+ iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
	727	+ <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
	728	+ <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
	729	+ <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
	730	+ <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
	731	+ <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
	732	+ <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
	733	+ <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
	734	+ };
	735	+
	736	+ dmac1: dma-controller@e7300000 {
	737	+ compatible = "renesas,dmac-r8a77990",
	738	+ "renesas,rcar-dmac";
	739	+ reg = <0 0xe7300000 0 0x10000>;
	740	+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	741	+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	742	+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
	743	+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	744	+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	745	+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
	746	+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
	747	+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
	748	+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
	749	+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	750	+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	751	+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
	752	+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	753	+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	754	+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	755	+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	756	+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	757	+ interrupt-names = "error",
	758	+ "ch0", "ch1", "ch2", "ch3",
	759	+ "ch4", "ch5", "ch6", "ch7",
	760	+ "ch8", "ch9", "ch10", "ch11",
	761	+ "ch12", "ch13", "ch14", "ch15";
	762	+ clocks = <&cpg CPG_MOD 218>;
	763	+ clock-names = "fck";
	764	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	765	+ resets = <&cpg 218>;
	766	+ #dma-cells = <1>;
	767	+ dma-channels = <16>;
	768	+ iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
	769	+ <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
	770	+ <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
	771	+ <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
	772	+ <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
	773	+ <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
	774	+ <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
	775	+ <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
	776	+ };
	777	+
	778	+ dmac2: dma-controller@e7310000 {
	779	+ compatible = "renesas,dmac-r8a77990",
	780	+ "renesas,rcar-dmac";
	781	+ reg = <0 0xe7310000 0 0x10000>;
	782	+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	783	+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	784	+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	785	+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	786	+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	787	+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	788	+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	789	+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	790	+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	791	+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
	792	+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
	793	+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
	794	+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
	795	+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	796	+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	797	+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	798	+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	799	+ interrupt-names = "error",
	800	+ "ch0", "ch1", "ch2", "ch3",
	801	+ "ch4", "ch5", "ch6", "ch7",
	802	+ "ch8", "ch9", "ch10", "ch11",
	803	+ "ch12", "ch13", "ch14", "ch15";
	804	+ clocks = <&cpg CPG_MOD 217>;
	805	+ clock-names = "fck";
	806	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	807	+ resets = <&cpg 217>;
	808	+ #dma-cells = <1>;
	809	+ dma-channels = <16>;
	810	+ iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
	811	+ <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
	812	+ <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
	813	+ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
	814	+ <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
	815	+ <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
	816	+ <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
	817	+ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
	818	+ };
	819	+
	820	+ ipmmu_ds0: iommu@e6740000 {
215	821	compatible = "renesas,ipmmu-r8a77990";
216	822	reg = <0 0xe6740000 0 0x1000>;
217	823	renesas,ipmmu-main = <&ipmmu_mm 0>;
..	..	@@ -219,7 +825,7 @@
219	825	#iommu-cells = <1>;
220	826	};
221	827
222		- ipmmu_ds1: mmu@e7740000 {
	828	+ ipmmu_ds1: iommu@e7740000 {
223	829	compatible = "renesas,ipmmu-r8a77990";
224	830	reg = <0 0xe7740000 0 0x1000>;
225	831	renesas,ipmmu-main = <&ipmmu_mm 1>;
..	..	@@ -227,7 +833,7 @@
227	833	#iommu-cells = <1>;
228	834	};
229	835
230		- ipmmu_hc: mmu@e6570000 {
	836	+ ipmmu_hc: iommu@e6570000 {
231	837	compatible = "renesas,ipmmu-r8a77990";
232	838	reg = <0 0xe6570000 0 0x1000>;
233	839	renesas,ipmmu-main = <&ipmmu_mm 2>;
..	..	@@ -235,7 +841,7 @@
235	841	#iommu-cells = <1>;
236	842	};
237	843
238		- ipmmu_mm: mmu@e67b0000 {
	844	+ ipmmu_mm: iommu@e67b0000 {
239	845	compatible = "renesas,ipmmu-r8a77990";
240	846	reg = <0 0xe67b0000 0 0x1000>;
241	847	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
..	..	@@ -244,7 +850,7 @@
244	850	#iommu-cells = <1>;
245	851	};
246	852
247		- ipmmu_mp: mmu@ec670000 {
	853	+ ipmmu_mp: iommu@ec670000 {
248	854	compatible = "renesas,ipmmu-r8a77990";
249	855	reg = <0 0xec670000 0 0x1000>;
250	856	renesas,ipmmu-main = <&ipmmu_mm 4>;
..	..	@@ -252,7 +858,7 @@
252	858	#iommu-cells = <1>;
253	859	};
254	860
255		- ipmmu_pv0: mmu@fd800000 {
	861	+ ipmmu_pv0: iommu@fd800000 {
256	862	compatible = "renesas,ipmmu-r8a77990";
257	863	reg = <0 0xfd800000 0 0x1000>;
258	864	renesas,ipmmu-main = <&ipmmu_mm 6>;
..	..	@@ -260,7 +866,7 @@
260	866	#iommu-cells = <1>;
261	867	};
262	868
263		- ipmmu_rt: mmu@ffc80000 {
	869	+ ipmmu_rt: iommu@ffc80000 {
264	870	compatible = "renesas,ipmmu-r8a77990";
265	871	reg = <0 0xffc80000 0 0x1000>;
266	872	renesas,ipmmu-main = <&ipmmu_mm 10>;
..	..	@@ -268,7 +874,7 @@
268	874	#iommu-cells = <1>;
269	875	};
270	876
271		- ipmmu_vc0: mmu@fe6b0000 {
	877	+ ipmmu_vc0: iommu@fe6b0000 {
272	878	compatible = "renesas,ipmmu-r8a77990";
273	879	reg = <0 0xfe6b0000 0 0x1000>;
274	880	renesas,ipmmu-main = <&ipmmu_mm 12>;
..	..	@@ -276,7 +882,7 @@
276	882	#iommu-cells = <1>;
277	883	};
278	884
279		- ipmmu_vi0: mmu@febd0000 {
	885	+ ipmmu_vi0: iommu@febd0000 {
280	886	compatible = "renesas,ipmmu-r8a77990";
281	887	reg = <0 0xfebd0000 0 0x1000>;
282	888	renesas,ipmmu-main = <&ipmmu_mm 14>;
..	..	@@ -284,7 +890,7 @@
284	890	#iommu-cells = <1>;
285	891	};
286	892
287		- ipmmu_vp0: mmu@fe990000 {
	893	+ ipmmu_vp0: iommu@fe990000 {
288	894	compatible = "renesas,ipmmu-r8a77990";
289	895	reg = <0 0xfe990000 0 0x1000>;
290	896	renesas,ipmmu-main = <&ipmmu_mm 16>;
..	..	@@ -329,11 +935,173 @@
329	935	"ch20", "ch21", "ch22", "ch23",
330	936	"ch24";
331	937	clocks = <&cpg CPG_MOD 812>;
332		- power-domains = <&sysc 32>;
	938	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
333	939	resets = <&cpg 812>;
334	940	phy-mode = "rgmii";
	941	+ iommus = <&ipmmu_ds0 16>;
335	942	#address-cells = <1>;
336	943	#size-cells = <0>;
	944	+ status = "disabled";
	945	+ };
	946	+
	947	+ can0: can@e6c30000 {
	948	+ compatible = "renesas,can-r8a77990",
	949	+ "renesas,rcar-gen3-can";
	950	+ reg = <0 0xe6c30000 0 0x1000>;
	951	+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	952	+ clocks = <&cpg CPG_MOD 916>,
	953	+ <&cpg CPG_CORE R8A77990_CLK_CANFD>,
	954	+ <&can_clk>;
	955	+ clock-names = "clkp1", "clkp2", "can_clk";
	956	+ assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
	957	+ assigned-clock-rates = <40000000>;
	958	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	959	+ resets = <&cpg 916>;
	960	+ status = "disabled";
	961	+ };
	962	+
	963	+ can1: can@e6c38000 {
	964	+ compatible = "renesas,can-r8a77990",
	965	+ "renesas,rcar-gen3-can";
	966	+ reg = <0 0xe6c38000 0 0x1000>;
	967	+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	968	+ clocks = <&cpg CPG_MOD 915>,
	969	+ <&cpg CPG_CORE R8A77990_CLK_CANFD>,
	970	+ <&can_clk>;
	971	+ clock-names = "clkp1", "clkp2", "can_clk";
	972	+ assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
	973	+ assigned-clock-rates = <40000000>;
	974	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	975	+ resets = <&cpg 915>;
	976	+ status = "disabled";
	977	+ };
	978	+
	979	+ canfd: can@e66c0000 {
	980	+ compatible = "renesas,r8a77990-canfd",
	981	+ "renesas,rcar-gen3-canfd";
	982	+ reg = <0 0xe66c0000 0 0x8000>;
	983	+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
	984	+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	985	+ clocks = <&cpg CPG_MOD 914>,
	986	+ <&cpg CPG_CORE R8A77990_CLK_CANFD>,
	987	+ <&can_clk>;
	988	+ clock-names = "fck", "canfd", "can_clk";
	989	+ assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
	990	+ assigned-clock-rates = <40000000>;
	991	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	992	+ resets = <&cpg 914>;
	993	+ status = "disabled";
	994	+
	995	+ channel0 {
	996	+ status = "disabled";
	997	+ };
	998	+
	999	+ channel1 {
	1000	+ status = "disabled";
	1001	+ };
	1002	+ };
	1003	+
	1004	+ pwm0: pwm@e6e30000 {
	1005	+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	1006	+ reg = <0 0xe6e30000 0 0x8>;
	1007	+ clocks = <&cpg CPG_MOD 523>;
	1008	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1009	+ resets = <&cpg 523>;
	1010	+ #pwm-cells = <2>;
	1011	+ status = "disabled";
	1012	+ };
	1013	+
	1014	+ pwm1: pwm@e6e31000 {
	1015	+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	1016	+ reg = <0 0xe6e31000 0 0x8>;
	1017	+ clocks = <&cpg CPG_MOD 523>;
	1018	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1019	+ resets = <&cpg 523>;
	1020	+ #pwm-cells = <2>;
	1021	+ status = "disabled";
	1022	+ };
	1023	+
	1024	+ pwm2: pwm@e6e32000 {
	1025	+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	1026	+ reg = <0 0xe6e32000 0 0x8>;
	1027	+ clocks = <&cpg CPG_MOD 523>;
	1028	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1029	+ resets = <&cpg 523>;
	1030	+ #pwm-cells = <2>;
	1031	+ status = "disabled";
	1032	+ };
	1033	+
	1034	+ pwm3: pwm@e6e33000 {
	1035	+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	1036	+ reg = <0 0xe6e33000 0 0x8>;
	1037	+ clocks = <&cpg CPG_MOD 523>;
	1038	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1039	+ resets = <&cpg 523>;
	1040	+ #pwm-cells = <2>;
	1041	+ status = "disabled";
	1042	+ };
	1043	+
	1044	+ pwm4: pwm@e6e34000 {
	1045	+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	1046	+ reg = <0 0xe6e34000 0 0x8>;
	1047	+ clocks = <&cpg CPG_MOD 523>;
	1048	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1049	+ resets = <&cpg 523>;
	1050	+ #pwm-cells = <2>;
	1051	+ status = "disabled";
	1052	+ };
	1053	+
	1054	+ pwm5: pwm@e6e35000 {
	1055	+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	1056	+ reg = <0 0xe6e35000 0 0x8>;
	1057	+ clocks = <&cpg CPG_MOD 523>;
	1058	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1059	+ resets = <&cpg 523>;
	1060	+ #pwm-cells = <2>;
	1061	+ status = "disabled";
	1062	+ };
	1063	+
	1064	+ pwm6: pwm@e6e36000 {
	1065	+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
	1066	+ reg = <0 0xe6e36000 0 0x8>;
	1067	+ clocks = <&cpg CPG_MOD 523>;
	1068	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1069	+ resets = <&cpg 523>;
	1070	+ #pwm-cells = <2>;
	1071	+ status = "disabled";
	1072	+ };
	1073	+
	1074	+ scif0: serial@e6e60000 {
	1075	+ compatible = "renesas,scif-r8a77990",
	1076	+ "renesas,rcar-gen3-scif", "renesas,scif";
	1077	+ reg = <0 0xe6e60000 0 64>;
	1078	+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	1079	+ clocks = <&cpg CPG_MOD 207>,
	1080	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	1081	+ <&scif_clk>;
	1082	+ clock-names = "fck", "brg_int", "scif_clk";
	1083	+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	1084	+ <&dmac2 0x51>, <&dmac2 0x50>;
	1085	+ dma-names = "tx", "rx", "tx", "rx";
	1086	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1087	+ resets = <&cpg 207>;
	1088	+ status = "disabled";
	1089	+ };
	1090	+
	1091	+ scif1: serial@e6e68000 {
	1092	+ compatible = "renesas,scif-r8a77990",
	1093	+ "renesas,rcar-gen3-scif", "renesas,scif";
	1094	+ reg = <0 0xe6e68000 0 64>;
	1095	+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	1096	+ clocks = <&cpg CPG_MOD 206>,
	1097	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	1098	+ <&scif_clk>;
	1099	+ clock-names = "fck", "brg_int", "scif_clk";
	1100	+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	1101	+ <&dmac2 0x53>, <&dmac2 0x52>;
	1102	+ dma-names = "tx", "rx", "tx", "rx";
	1103	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1104	+ resets = <&cpg 206>;
337	1105	status = "disabled";
338	1106	};
339	1107
..	..	@@ -342,11 +1110,549 @@
342	1110	"renesas,rcar-gen3-scif", "renesas,scif";
343	1111	reg = <0 0xe6e88000 0 64>;
344	1112	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
345		- clocks = <&cpg CPG_MOD 310>;
346		- clock-names = "fck";
347		- power-domains = <&sysc 32>;
	1113	+ clocks = <&cpg CPG_MOD 310>,
	1114	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	1115	+ <&scif_clk>;
	1116	+ clock-names = "fck", "brg_int", "scif_clk";
	1117	+ dmas = <&dmac1 0x13>, <&dmac1 0x12>,
	1118	+ <&dmac2 0x13>, <&dmac2 0x12>;
	1119	+ dma-names = "tx", "rx", "tx", "rx";
	1120	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
348	1121	resets = <&cpg 310>;
349	1122	status = "disabled";
	1123	+ };
	1124	+
	1125	+ scif3: serial@e6c50000 {
	1126	+ compatible = "renesas,scif-r8a77990",
	1127	+ "renesas,rcar-gen3-scif", "renesas,scif";
	1128	+ reg = <0 0xe6c50000 0 64>;
	1129	+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	1130	+ clocks = <&cpg CPG_MOD 204>,
	1131	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	1132	+ <&scif_clk>;
	1133	+ clock-names = "fck", "brg_int", "scif_clk";
	1134	+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	1135	+ dma-names = "tx", "rx";
	1136	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1137	+ resets = <&cpg 204>;
	1138	+ status = "disabled";
	1139	+ };
	1140	+
	1141	+ scif4: serial@e6c40000 {
	1142	+ compatible = "renesas,scif-r8a77990",
	1143	+ "renesas,rcar-gen3-scif", "renesas,scif";
	1144	+ reg = <0 0xe6c40000 0 64>;
	1145	+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	1146	+ clocks = <&cpg CPG_MOD 203>,
	1147	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	1148	+ <&scif_clk>;
	1149	+ clock-names = "fck", "brg_int", "scif_clk";
	1150	+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	1151	+ dma-names = "tx", "rx";
	1152	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1153	+ resets = <&cpg 203>;
	1154	+ status = "disabled";
	1155	+ };
	1156	+
	1157	+ scif5: serial@e6f30000 {
	1158	+ compatible = "renesas,scif-r8a77990",
	1159	+ "renesas,rcar-gen3-scif", "renesas,scif";
	1160	+ reg = <0 0xe6f30000 0 64>;
	1161	+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	1162	+ clocks = <&cpg CPG_MOD 202>,
	1163	+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
	1164	+ <&scif_clk>;
	1165	+ clock-names = "fck", "brg_int", "scif_clk";
	1166	+ dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
	1167	+ dma-names = "tx", "rx";
	1168	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1169	+ resets = <&cpg 202>;
	1170	+ status = "disabled";
	1171	+ };
	1172	+
	1173	+ msiof0: spi@e6e90000 {
	1174	+ compatible = "renesas,msiof-r8a77990",
	1175	+ "renesas,rcar-gen3-msiof";
	1176	+ reg = <0 0xe6e90000 0 0x0064>;
	1177	+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	1178	+ clocks = <&cpg CPG_MOD 211>;
	1179	+ dmas = <&dmac1 0x41>, <&dmac1 0x40>,
	1180	+ <&dmac2 0x41>, <&dmac2 0x40>;
	1181	+ dma-names = "tx", "rx", "tx", "rx";
	1182	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1183	+ resets = <&cpg 211>;
	1184	+ #address-cells = <1>;
	1185	+ #size-cells = <0>;
	1186	+ status = "disabled";
	1187	+ };
	1188	+
	1189	+ msiof1: spi@e6ea0000 {
	1190	+ compatible = "renesas,msiof-r8a77990",
	1191	+ "renesas,rcar-gen3-msiof";
	1192	+ reg = <0 0xe6ea0000 0 0x0064>;
	1193	+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	1194	+ clocks = <&cpg CPG_MOD 210>;
	1195	+ dmas = <&dmac0 0x43>, <&dmac0 0x42>;
	1196	+ dma-names = "tx", "rx";
	1197	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1198	+ resets = <&cpg 210>;
	1199	+ #address-cells = <1>;
	1200	+ #size-cells = <0>;
	1201	+ status = "disabled";
	1202	+ };
	1203	+
	1204	+ msiof2: spi@e6c00000 {
	1205	+ compatible = "renesas,msiof-r8a77990",
	1206	+ "renesas,rcar-gen3-msiof";
	1207	+ reg = <0 0xe6c00000 0 0x0064>;
	1208	+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
	1209	+ clocks = <&cpg CPG_MOD 209>;
	1210	+ dmas = <&dmac0 0x45>, <&dmac0 0x44>;
	1211	+ dma-names = "tx", "rx";
	1212	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1213	+ resets = <&cpg 209>;
	1214	+ #address-cells = <1>;
	1215	+ #size-cells = <0>;
	1216	+ status = "disabled";
	1217	+ };
	1218	+
	1219	+ msiof3: spi@e6c10000 {
	1220	+ compatible = "renesas,msiof-r8a77990",
	1221	+ "renesas,rcar-gen3-msiof";
	1222	+ reg = <0 0xe6c10000 0 0x0064>;
	1223	+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
	1224	+ clocks = <&cpg CPG_MOD 208>;
	1225	+ dmas = <&dmac0 0x47>, <&dmac0 0x46>;
	1226	+ dma-names = "tx", "rx";
	1227	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1228	+ resets = <&cpg 208>;
	1229	+ #address-cells = <1>;
	1230	+ #size-cells = <0>;
	1231	+ status = "disabled";
	1232	+ };
	1233	+
	1234	+ vin4: video@e6ef4000 {
	1235	+ compatible = "renesas,vin-r8a77990";
	1236	+ reg = <0 0xe6ef4000 0 0x1000>;
	1237	+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	1238	+ clocks = <&cpg CPG_MOD 807>;
	1239	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1240	+ resets = <&cpg 807>;
	1241	+ renesas,id = <4>;
	1242	+ status = "disabled";
	1243	+
	1244	+ ports {
	1245	+ #address-cells = <1>;
	1246	+ #size-cells = <0>;
	1247	+
	1248	+ port@1 {
	1249	+ #address-cells = <1>;
	1250	+ #size-cells = <0>;
	1251	+
	1252	+ reg = <1>;
	1253	+
	1254	+ vin4csi40: endpoint@2 {
	1255	+ reg = <2>;
	1256	+ remote-endpoint= <&csi40vin4>;
	1257	+ };
	1258	+ };
	1259	+ };
	1260	+ };
	1261	+
	1262	+ vin5: video@e6ef5000 {
	1263	+ compatible = "renesas,vin-r8a77990";
	1264	+ reg = <0 0xe6ef5000 0 0x1000>;
	1265	+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	1266	+ clocks = <&cpg CPG_MOD 806>;
	1267	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1268	+ resets = <&cpg 806>;
	1269	+ renesas,id = <5>;
	1270	+ status = "disabled";
	1271	+
	1272	+ ports {
	1273	+ #address-cells = <1>;
	1274	+ #size-cells = <0>;
	1275	+
	1276	+ port@1 {
	1277	+ #address-cells = <1>;
	1278	+ #size-cells = <0>;
	1279	+
	1280	+ reg = <1>;
	1281	+
	1282	+ vin5csi40: endpoint@2 {
	1283	+ reg = <2>;
	1284	+ remote-endpoint= <&csi40vin5>;
	1285	+ };
	1286	+ };
	1287	+ };
	1288	+ };
	1289	+
	1290	+ drif00: rif@e6f40000 {
	1291	+ compatible = "renesas,r8a77990-drif",
	1292	+ "renesas,rcar-gen3-drif";
	1293	+ reg = <0 0xe6f40000 0 0x84>;
	1294	+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	1295	+ clocks = <&cpg CPG_MOD 515>;
	1296	+ clock-names = "fck";
	1297	+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
	1298	+ dma-names = "rx", "rx";
	1299	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1300	+ resets = <&cpg 515>;
	1301	+ renesas,bonding = <&drif01>;
	1302	+ status = "disabled";
	1303	+ };
	1304	+
	1305	+ drif01: rif@e6f50000 {
	1306	+ compatible = "renesas,r8a77990-drif",
	1307	+ "renesas,rcar-gen3-drif";
	1308	+ reg = <0 0xe6f50000 0 0x84>;
	1309	+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	1310	+ clocks = <&cpg CPG_MOD 514>;
	1311	+ clock-names = "fck";
	1312	+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
	1313	+ dma-names = "rx", "rx";
	1314	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1315	+ resets = <&cpg 514>;
	1316	+ renesas,bonding = <&drif00>;
	1317	+ status = "disabled";
	1318	+ };
	1319	+
	1320	+ drif10: rif@e6f60000 {
	1321	+ compatible = "renesas,r8a77990-drif",
	1322	+ "renesas,rcar-gen3-drif";
	1323	+ reg = <0 0xe6f60000 0 0x84>;
	1324	+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	1325	+ clocks = <&cpg CPG_MOD 513>;
	1326	+ clock-names = "fck";
	1327	+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
	1328	+ dma-names = "rx", "rx";
	1329	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1330	+ resets = <&cpg 513>;
	1331	+ renesas,bonding = <&drif11>;
	1332	+ status = "disabled";
	1333	+ };
	1334	+
	1335	+ drif11: rif@e6f70000 {
	1336	+ compatible = "renesas,r8a77990-drif",
	1337	+ "renesas,rcar-gen3-drif";
	1338	+ reg = <0 0xe6f70000 0 0x84>;
	1339	+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	1340	+ clocks = <&cpg CPG_MOD 512>;
	1341	+ clock-names = "fck";
	1342	+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
	1343	+ dma-names = "rx", "rx";
	1344	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1345	+ resets = <&cpg 512>;
	1346	+ renesas,bonding = <&drif10>;
	1347	+ status = "disabled";
	1348	+ };
	1349	+
	1350	+ drif20: rif@e6f80000 {
	1351	+ compatible = "renesas,r8a77990-drif",
	1352	+ "renesas,rcar-gen3-drif";
	1353	+ reg = <0 0xe6f80000 0 0x84>;
	1354	+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	1355	+ clocks = <&cpg CPG_MOD 511>;
	1356	+ clock-names = "fck";
	1357	+ dmas = <&dmac0 0x28>;
	1358	+ dma-names = "rx";
	1359	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1360	+ resets = <&cpg 511>;
	1361	+ renesas,bonding = <&drif21>;
	1362	+ status = "disabled";
	1363	+ };
	1364	+
	1365	+ drif21: rif@e6f90000 {
	1366	+ compatible = "renesas,r8a77990-drif",
	1367	+ "renesas,rcar-gen3-drif";
	1368	+ reg = <0 0xe6f90000 0 0x84>;
	1369	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	1370	+ clocks = <&cpg CPG_MOD 510>;
	1371	+ clock-names = "fck";
	1372	+ dmas = <&dmac0 0x2a>;
	1373	+ dma-names = "rx";
	1374	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1375	+ resets = <&cpg 510>;
	1376	+ renesas,bonding = <&drif20>;
	1377	+ status = "disabled";
	1378	+ };
	1379	+
	1380	+ drif30: rif@e6fa0000 {
	1381	+ compatible = "renesas,r8a77990-drif",
	1382	+ "renesas,rcar-gen3-drif";
	1383	+ reg = <0 0xe6fa0000 0 0x84>;
	1384	+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	1385	+ clocks = <&cpg CPG_MOD 509>;
	1386	+ clock-names = "fck";
	1387	+ dmas = <&dmac0 0x2c>;
	1388	+ dma-names = "rx";
	1389	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1390	+ resets = <&cpg 509>;
	1391	+ renesas,bonding = <&drif31>;
	1392	+ status = "disabled";
	1393	+ };
	1394	+
	1395	+ drif31: rif@e6fb0000 {
	1396	+ compatible = "renesas,r8a77990-drif",
	1397	+ "renesas,rcar-gen3-drif";
	1398	+ reg = <0 0xe6fb0000 0 0x84>;
	1399	+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	1400	+ clocks = <&cpg CPG_MOD 508>;
	1401	+ clock-names = "fck";
	1402	+ dmas = <&dmac0 0x2e>;
	1403	+ dma-names = "rx";
	1404	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1405	+ resets = <&cpg 508>;
	1406	+ renesas,bonding = <&drif30>;
	1407	+ status = "disabled";
	1408	+ };
	1409	+
	1410	+ rcar_sound: sound@ec500000 {
	1411	+ /*
	1412	+ * #sound-dai-cells is required
	1413	+ *
	1414	+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	1415	+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	1416	+ */
	1417	+ /*
	1418	+ * #clock-cells is required for audio_clkout0/1/2/3
	1419	+ *
	1420	+ * clkout : #clock-cells = <0>; <&rcar_sound>;
	1421	+ * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
	1422	+ */
	1423	+ compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
	1424	+ reg = <0 0xec500000 0 0x1000>, /* SCU */
	1425	+ <0 0xec5a0000 0 0x100>, /* ADG */
	1426	+ <0 0xec540000 0 0x1000>, /* SSIU */
	1427	+ <0 0xec541000 0 0x280>, /* SSI */
	1428	+ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
	1429	+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
	1430	+
	1431	+ clocks = <&cpg CPG_MOD 1005>,
	1432	+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	1433	+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	1434	+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	1435	+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	1436	+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	1437	+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	1438	+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	1439	+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	1440	+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	1441	+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	1442	+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	1443	+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	1444	+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	1445	+ <&audio_clk_a>, <&audio_clk_b>,
	1446	+ <&audio_clk_c>,
	1447	+ <&cpg CPG_CORE R8A77990_CLK_ZA2>;
	1448	+ clock-names = "ssi-all",
	1449	+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
	1450	+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
	1451	+ "ssi.1", "ssi.0",
	1452	+ "src.9", "src.8", "src.7", "src.6",
	1453	+ "src.5", "src.4", "src.3", "src.2",
	1454	+ "src.1", "src.0",
	1455	+ "mix.1", "mix.0",
	1456	+ "ctu.1", "ctu.0",
	1457	+ "dvc.0", "dvc.1",
	1458	+ "clk_a", "clk_b", "clk_c", "clk_i";
	1459	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1460	+ resets = <&cpg 1005>,
	1461	+ <&cpg 1006>, <&cpg 1007>,
	1462	+ <&cpg 1008>, <&cpg 1009>,
	1463	+ <&cpg 1010>, <&cpg 1011>,
	1464	+ <&cpg 1012>, <&cpg 1013>,
	1465	+ <&cpg 1014>, <&cpg 1015>;
	1466	+ reset-names = "ssi-all",
	1467	+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
	1468	+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
	1469	+ "ssi.1", "ssi.0";
	1470	+ status = "disabled";
	1471	+
	1472	+ rcar_sound,ctu {
	1473	+ ctu00: ctu-0 { };
	1474	+ ctu01: ctu-1 { };
	1475	+ ctu02: ctu-2 { };
	1476	+ ctu03: ctu-3 { };
	1477	+ ctu10: ctu-4 { };
	1478	+ ctu11: ctu-5 { };
	1479	+ ctu12: ctu-6 { };
	1480	+ ctu13: ctu-7 { };
	1481	+ };
	1482	+
	1483	+ rcar_sound,dvc {
	1484	+ dvc0: dvc-0 {
	1485	+ dmas = <&audma0 0xbc>;
	1486	+ dma-names = "tx";
	1487	+ };
	1488	+ dvc1: dvc-1 {
	1489	+ dmas = <&audma0 0xbe>;
	1490	+ dma-names = "tx";
	1491	+ };
	1492	+ };
	1493	+
	1494	+ rcar_sound,mix {
	1495	+ mix0: mix-0 { };
	1496	+ mix1: mix-1 { };
	1497	+ };
	1498	+
	1499	+ rcar_sound,src {
	1500	+ src0: src-0 {
	1501	+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
	1502	+ dmas = <&audma0 0x85>, <&audma0 0x9a>;
	1503	+ dma-names = "rx", "tx";
	1504	+ };
	1505	+ src1: src-1 {
	1506	+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	1507	+ dmas = <&audma0 0x87>, <&audma0 0x9c>;
	1508	+ dma-names = "rx", "tx";
	1509	+ };
	1510	+ src2: src-2 {
	1511	+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	1512	+ dmas = <&audma0 0x89>, <&audma0 0x9e>;
	1513	+ dma-names = "rx", "tx";
	1514	+ };
	1515	+ src3: src-3 {
	1516	+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	1517	+ dmas = <&audma0 0x8b>, <&audma0 0xa0>;
	1518	+ dma-names = "rx", "tx";
	1519	+ };
	1520	+ src4: src-4 {
	1521	+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	1522	+ dmas = <&audma0 0x8d>, <&audma0 0xb0>;
	1523	+ dma-names = "rx", "tx";
	1524	+ };
	1525	+ src5: src-5 {
	1526	+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	1527	+ dmas = <&audma0 0x8f>, <&audma0 0xb2>;
	1528	+ dma-names = "rx", "tx";
	1529	+ };
	1530	+ src6: src-6 {
	1531	+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	1532	+ dmas = <&audma0 0x91>, <&audma0 0xb4>;
	1533	+ dma-names = "rx", "tx";
	1534	+ };
	1535	+ src7: src-7 {
	1536	+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	1537	+ dmas = <&audma0 0x93>, <&audma0 0xb6>;
	1538	+ dma-names = "rx", "tx";
	1539	+ };
	1540	+ src8: src-8 {
	1541	+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	1542	+ dmas = <&audma0 0x95>, <&audma0 0xb8>;
	1543	+ dma-names = "rx", "tx";
	1544	+ };
	1545	+ src9: src-9 {
	1546	+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
	1547	+ dmas = <&audma0 0x97>, <&audma0 0xba>;
	1548	+ dma-names = "rx", "tx";
	1549	+ };
	1550	+ };
	1551	+
	1552	+ rcar_sound,ssi {
	1553	+ ssi0: ssi-0 {
	1554	+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
	1555	+ dmas = <&audma0 0x01>, <&audma0 0x02>,
	1556	+ <&audma0 0x15>, <&audma0 0x16>;
	1557	+ dma-names = "rx", "tx", "rxu", "txu";
	1558	+ };
	1559	+ ssi1: ssi-1 {
	1560	+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
	1561	+ dmas = <&audma0 0x03>, <&audma0 0x04>,
	1562	+ <&audma0 0x49>, <&audma0 0x4a>;
	1563	+ dma-names = "rx", "tx", "rxu", "txu";
	1564	+ };
	1565	+ ssi2: ssi-2 {
	1566	+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
	1567	+ dmas = <&audma0 0x05>, <&audma0 0x06>,
	1568	+ <&audma0 0x63>, <&audma0 0x64>;
	1569	+ dma-names = "rx", "tx", "rxu", "txu";
	1570	+ };
	1571	+ ssi3: ssi-3 {
	1572	+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
	1573	+ dmas = <&audma0 0x07>, <&audma0 0x08>,
	1574	+ <&audma0 0x6f>, <&audma0 0x70>;
	1575	+ dma-names = "rx", "tx", "rxu", "txu";
	1576	+ };
	1577	+ ssi4: ssi-4 {
	1578	+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
	1579	+ dmas = <&audma0 0x09>, <&audma0 0x0a>,
	1580	+ <&audma0 0x71>, <&audma0 0x72>;
	1581	+ dma-names = "rx", "tx", "rxu", "txu";
	1582	+ };
	1583	+ ssi5: ssi-5 {
	1584	+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
	1585	+ dmas = <&audma0 0x0b>, <&audma0 0x0c>,
	1586	+ <&audma0 0x73>, <&audma0 0x74>;
	1587	+ dma-names = "rx", "tx", "rxu", "txu";
	1588	+ };
	1589	+ ssi6: ssi-6 {
	1590	+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
	1591	+ dmas = <&audma0 0x0d>, <&audma0 0x0e>,
	1592	+ <&audma0 0x75>, <&audma0 0x76>;
	1593	+ dma-names = "rx", "tx", "rxu", "txu";
	1594	+ };
	1595	+ ssi7: ssi-7 {
	1596	+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	1597	+ dmas = <&audma0 0x0f>, <&audma0 0x10>,
	1598	+ <&audma0 0x79>, <&audma0 0x7a>;
	1599	+ dma-names = "rx", "tx", "rxu", "txu";
	1600	+ };
	1601	+ ssi8: ssi-8 {
	1602	+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
	1603	+ dmas = <&audma0 0x11>, <&audma0 0x12>,
	1604	+ <&audma0 0x7b>, <&audma0 0x7c>;
	1605	+ dma-names = "rx", "tx", "rxu", "txu";
	1606	+ };
	1607	+ ssi9: ssi-9 {
	1608	+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
	1609	+ dmas = <&audma0 0x13>, <&audma0 0x14>,
	1610	+ <&audma0 0x7d>, <&audma0 0x7e>;
	1611	+ dma-names = "rx", "tx", "rxu", "txu";
	1612	+ };
	1613	+ };
	1614	+ };
	1615	+
	1616	+ audma0: dma-controller@ec700000 {
	1617	+ compatible = "renesas,dmac-r8a77990",
	1618	+ "renesas,rcar-dmac";
	1619	+ reg = <0 0xec700000 0 0x10000>;
	1620	+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
	1621	+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	1622	+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	1623	+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	1624	+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	1625	+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	1626	+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	1627	+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	1628	+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	1629	+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	1630	+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	1631	+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	1632	+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	1633	+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	1634	+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	1635	+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	1636	+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
	1637	+ interrupt-names = "error",
	1638	+ "ch0", "ch1", "ch2", "ch3",
	1639	+ "ch4", "ch5", "ch6", "ch7",
	1640	+ "ch8", "ch9", "ch10", "ch11",
	1641	+ "ch12", "ch13", "ch14", "ch15";
	1642	+ clocks = <&cpg CPG_MOD 502>;
	1643	+ clock-names = "fck";
	1644	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1645	+ resets = <&cpg 502>;
	1646	+ #dma-cells = <1>;
	1647	+ dma-channels = <16>;
	1648	+ iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
	1649	+ <&ipmmu_mp 2>, <&ipmmu_mp 3>,
	1650	+ <&ipmmu_mp 4>, <&ipmmu_mp 5>,
	1651	+ <&ipmmu_mp 6>, <&ipmmu_mp 7>,
	1652	+ <&ipmmu_mp 8>, <&ipmmu_mp 9>,
	1653	+ <&ipmmu_mp 10>, <&ipmmu_mp 11>,
	1654	+ <&ipmmu_mp 12>, <&ipmmu_mp 13>,
	1655	+ <&ipmmu_mp 14>, <&ipmmu_mp 15>;
350	1656	};
351	1657
352	1658	xhci0: usb@ee000000 {
..	..	@@ -360,15 +1666,26 @@
360	1666	status = "disabled";
361	1667	};
362	1668
	1669	+ usb3_peri0: usb@ee020000 {
	1670	+ compatible = "renesas,r8a77990-usb3-peri",
	1671	+ "renesas,rcar-gen3-usb3-peri";
	1672	+ reg = <0 0xee020000 0 0x400>;
	1673	+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	1674	+ clocks = <&cpg CPG_MOD 328>;
	1675	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1676	+ resets = <&cpg 328>;
	1677	+ status = "disabled";
	1678	+ };
	1679	+
363	1680	ohci0: usb@ee080000 {
364	1681	compatible = "generic-ohci";
365	1682	reg = <0 0xee080000 0 0x100>;
366	1683	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
367		- clocks = <&cpg CPG_MOD 703>;
368		- phys = <&usb2_phy0>;
	1684	+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	1685	+ phys = <&usb2_phy0 1>;
369	1686	phy-names = "usb";
370		- power-domains = <&sysc 32>;
371		- resets = <&cpg 703>;
	1687	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1688	+ resets = <&cpg 703>, <&cpg 704>;
372	1689	status = "disabled";
373	1690	};
374	1691
..	..	@@ -376,12 +1693,12 @@
376	1693	compatible = "generic-ehci";
377	1694	reg = <0 0xee080100 0 0x100>;
378	1695	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
379		- clocks = <&cpg CPG_MOD 703>;
380		- phys = <&usb2_phy0>;
	1696	+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	1697	+ phys = <&usb2_phy0 2>;
381	1698	phy-names = "usb";
382	1699	companion = <&ohci0>;
383		- power-domains = <&sysc 32>;
384		- resets = <&cpg 703>;
	1700	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1701	+ resets = <&cpg 703>, <&cpg 704>;
385	1702	status = "disabled";
386	1703	};
387	1704
..	..	@@ -390,10 +1707,49 @@
390	1707	"renesas,rcar-gen3-usb2-phy";
391	1708	reg = <0 0xee080200 0 0x700>;
392	1709	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
393		- clocks = <&cpg CPG_MOD 703>;
394		- power-domains = <&sysc 32>;
395		- resets = <&cpg 703>;
396		- #phy-cells = <0>;
	1710	+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
	1711	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1712	+ resets = <&cpg 703>, <&cpg 704>;
	1713	+ #phy-cells = <1>;
	1714	+ status = "disabled";
	1715	+ };
	1716	+
	1717	+ sdhi0: mmc@ee100000 {
	1718	+ compatible = "renesas,sdhi-r8a77990",
	1719	+ "renesas,rcar-gen3-sdhi";
	1720	+ reg = <0 0xee100000 0 0x2000>;
	1721	+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	1722	+ clocks = <&cpg CPG_MOD 314>;
	1723	+ max-frequency = <200000000>;
	1724	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1725	+ resets = <&cpg 314>;
	1726	+ iommus = <&ipmmu_ds1 32>;
	1727	+ status = "disabled";
	1728	+ };
	1729	+
	1730	+ sdhi1: mmc@ee120000 {
	1731	+ compatible = "renesas,sdhi-r8a77990",
	1732	+ "renesas,rcar-gen3-sdhi";
	1733	+ reg = <0 0xee120000 0 0x2000>;
	1734	+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
	1735	+ clocks = <&cpg CPG_MOD 313>;
	1736	+ max-frequency = <200000000>;
	1737	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1738	+ resets = <&cpg 313>;
	1739	+ iommus = <&ipmmu_ds1 33>;
	1740	+ status = "disabled";
	1741	+ };
	1742	+
	1743	+ sdhi3: mmc@ee160000 {
	1744	+ compatible = "renesas,sdhi-r8a77990",
	1745	+ "renesas,rcar-gen3-sdhi";
	1746	+ reg = <0 0xee160000 0 0x2000>;
	1747	+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	1748	+ clocks = <&cpg CPG_MOD 311>;
	1749	+ max-frequency = <200000000>;
	1750	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1751	+ resets = <&cpg 311>;
	1752	+ iommus = <&ipmmu_ds1 35>;
397	1753	status = "disabled";
398	1754	};
399	1755
..	..	@@ -410,8 +1766,257 @@
410	1766	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
411	1767	clocks = <&cpg CPG_MOD 408>;
412	1768	clock-names = "clk";
413		- power-domains = <&sysc 32>;
	1769	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
414	1770	resets = <&cpg 408>;
	1771	+ };
	1772	+
	1773	+ pciec0: pcie@fe000000 {
	1774	+ compatible = "renesas,pcie-r8a77990",
	1775	+ "renesas,pcie-rcar-gen3";
	1776	+ reg = <0 0xfe000000 0 0x80000>;
	1777	+ #address-cells = <3>;
	1778	+ #size-cells = <2>;
	1779	+ bus-range = <0x00 0xff>;
	1780	+ device_type = "pci";
	1781	+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
	1782	+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
	1783	+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
	1784	+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
	1785	+ /* Map all possible DDR as inbound ranges */
	1786	+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
	1787	+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	1788	+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	1789	+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	1790	+ #interrupt-cells = <1>;
	1791	+ interrupt-map-mask = <0 0 0 0>;
	1792	+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	1793	+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
	1794	+ clock-names = "pcie", "pcie_bus";
	1795	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1796	+ resets = <&cpg 319>;
	1797	+ status = "disabled";
	1798	+ };
	1799	+
	1800	+ vspb0: vsp@fe960000 {
	1801	+ compatible = "renesas,vsp2";
	1802	+ reg = <0 0xfe960000 0 0x8000>;
	1803	+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	1804	+ clocks = <&cpg CPG_MOD 626>;
	1805	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1806	+ resets = <&cpg 626>;
	1807	+ renesas,fcp = <&fcpvb0>;
	1808	+ };
	1809	+
	1810	+ fcpvb0: fcp@fe96f000 {
	1811	+ compatible = "renesas,fcpv";
	1812	+ reg = <0 0xfe96f000 0 0x200>;
	1813	+ clocks = <&cpg CPG_MOD 607>;
	1814	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1815	+ resets = <&cpg 607>;
	1816	+ iommus = <&ipmmu_vp0 5>;
	1817	+ };
	1818	+
	1819	+ vspi0: vsp@fe9a0000 {
	1820	+ compatible = "renesas,vsp2";
	1821	+ reg = <0 0xfe9a0000 0 0x8000>;
	1822	+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	1823	+ clocks = <&cpg CPG_MOD 631>;
	1824	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1825	+ resets = <&cpg 631>;
	1826	+ renesas,fcp = <&fcpvi0>;
	1827	+ };
	1828	+
	1829	+ fcpvi0: fcp@fe9af000 {
	1830	+ compatible = "renesas,fcpv";
	1831	+ reg = <0 0xfe9af000 0 0x200>;
	1832	+ clocks = <&cpg CPG_MOD 611>;
	1833	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1834	+ resets = <&cpg 611>;
	1835	+ iommus = <&ipmmu_vp0 8>;
	1836	+ };
	1837	+
	1838	+ vspd0: vsp@fea20000 {
	1839	+ compatible = "renesas,vsp2";
	1840	+ reg = <0 0xfea20000 0 0x7000>;
	1841	+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
	1842	+ clocks = <&cpg CPG_MOD 623>;
	1843	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1844	+ resets = <&cpg 623>;
	1845	+ renesas,fcp = <&fcpvd0>;
	1846	+ };
	1847	+
	1848	+ fcpvd0: fcp@fea27000 {
	1849	+ compatible = "renesas,fcpv";
	1850	+ reg = <0 0xfea27000 0 0x200>;
	1851	+ clocks = <&cpg CPG_MOD 603>;
	1852	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1853	+ resets = <&cpg 603>;
	1854	+ iommus = <&ipmmu_vi0 8>;
	1855	+ };
	1856	+
	1857	+ vspd1: vsp@fea28000 {
	1858	+ compatible = "renesas,vsp2";
	1859	+ reg = <0 0xfea28000 0 0x7000>;
	1860	+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
	1861	+ clocks = <&cpg CPG_MOD 622>;
	1862	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1863	+ resets = <&cpg 622>;
	1864	+ renesas,fcp = <&fcpvd1>;
	1865	+ };
	1866	+
	1867	+ fcpvd1: fcp@fea2f000 {
	1868	+ compatible = "renesas,fcpv";
	1869	+ reg = <0 0xfea2f000 0 0x200>;
	1870	+ clocks = <&cpg CPG_MOD 602>;
	1871	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1872	+ resets = <&cpg 602>;
	1873	+ iommus = <&ipmmu_vi0 9>;
	1874	+ };
	1875	+
	1876	+ cmm0: cmm@fea40000 {
	1877	+ compatible = "renesas,r8a77990-cmm",
	1878	+ "renesas,rcar-gen3-cmm";
	1879	+ reg = <0 0xfea40000 0 0x1000>;
	1880	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1881	+ clocks = <&cpg CPG_MOD 711>;
	1882	+ resets = <&cpg 711>;
	1883	+ };
	1884	+
	1885	+ cmm1: cmm@fea50000 {
	1886	+ compatible = "renesas,r8a77990-cmm",
	1887	+ "renesas,rcar-gen3-cmm";
	1888	+ reg = <0 0xfea50000 0 0x1000>;
	1889	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1890	+ clocks = <&cpg CPG_MOD 710>;
	1891	+ resets = <&cpg 710>;
	1892	+ };
	1893	+
	1894	+ csi40: csi2@feaa0000 {
	1895	+ compatible = "renesas,r8a77990-csi2";
	1896	+ reg = <0 0xfeaa0000 0 0x10000>;
	1897	+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
	1898	+ clocks = <&cpg CPG_MOD 716>;
	1899	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1900	+ resets = <&cpg 716>;
	1901	+ status = "disabled";
	1902	+
	1903	+ ports {
	1904	+ #address-cells = <1>;
	1905	+ #size-cells = <0>;
	1906	+
	1907	+ port@1 {
	1908	+ #address-cells = <1>;
	1909	+ #size-cells = <0>;
	1910	+
	1911	+ reg = <1>;
	1912	+
	1913	+ csi40vin4: endpoint@0 {
	1914	+ reg = <0>;
	1915	+ remote-endpoint = <&vin4csi40>;
	1916	+ };
	1917	+ csi40vin5: endpoint@1 {
	1918	+ reg = <1>;
	1919	+ remote-endpoint = <&vin5csi40>;
	1920	+ };
	1921	+ };
	1922	+ };
	1923	+ };
	1924	+
	1925	+ du: display@feb00000 {
	1926	+ compatible = "renesas,du-r8a77990";
	1927	+ reg = <0 0xfeb00000 0 0x40000>;
	1928	+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	1929	+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	1930	+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
	1931	+ clock-names = "du.0", "du.1";
	1932	+ resets = <&cpg 724>;
	1933	+ reset-names = "du.0";
	1934	+
	1935	+ renesas,cmms = <&cmm0>, <&cmm1>;
	1936	+ renesas,vsps = <&vspd0 0>, <&vspd1 0>;
	1937	+
	1938	+ status = "disabled";
	1939	+
	1940	+ ports {
	1941	+ #address-cells = <1>;
	1942	+ #size-cells = <0>;
	1943	+
	1944	+ port@0 {
	1945	+ reg = <0>;
	1946	+ du_out_rgb: endpoint {
	1947	+ };
	1948	+ };
	1949	+
	1950	+ port@1 {
	1951	+ reg = <1>;
	1952	+ du_out_lvds0: endpoint {
	1953	+ remote-endpoint = <&lvds0_in>;
	1954	+ };
	1955	+ };
	1956	+
	1957	+ port@2 {
	1958	+ reg = <2>;
	1959	+ du_out_lvds1: endpoint {
	1960	+ remote-endpoint = <&lvds1_in>;
	1961	+ };
	1962	+ };
	1963	+ };
	1964	+ };
	1965	+
	1966	+ lvds0: lvds-encoder@feb90000 {
	1967	+ compatible = "renesas,r8a77990-lvds";
	1968	+ reg = <0 0xfeb90000 0 0x20>;
	1969	+ clocks = <&cpg CPG_MOD 727>;
	1970	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	1971	+ resets = <&cpg 727>;
	1972	+ status = "disabled";
	1973	+
	1974	+ renesas,companion = <&lvds1>;
	1975	+
	1976	+ ports {
	1977	+ #address-cells = <1>;
	1978	+ #size-cells = <0>;
	1979	+
	1980	+ port@0 {
	1981	+ reg = <0>;
	1982	+ lvds0_in: endpoint {
	1983	+ remote-endpoint = <&du_out_lvds0>;
	1984	+ };
	1985	+ };
	1986	+
	1987	+ port@1 {
	1988	+ reg = <1>;
	1989	+ lvds0_out: endpoint {
	1990	+ };
	1991	+ };
	1992	+ };
	1993	+ };
	1994	+
	1995	+ lvds1: lvds-encoder@feb90100 {
	1996	+ compatible = "renesas,r8a77990-lvds";
	1997	+ reg = <0 0xfeb90100 0 0x20>;
	1998	+ clocks = <&cpg CPG_MOD 727>;
	1999	+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
	2000	+ resets = <&cpg 726>;
	2001	+ status = "disabled";
	2002	+
	2003	+ ports {
	2004	+ #address-cells = <1>;
	2005	+ #size-cells = <0>;
	2006	+
	2007	+ port@0 {
	2008	+ reg = <0>;
	2009	+ lvds1_in: endpoint {
	2010	+ remote-endpoint = <&du_out_lvds1>;
	2011	+ };
	2012	+ };
	2013	+
	2014	+ port@1 {
	2015	+ reg = <1>;
	2016	+ lvds1_out: endpoint {
	2017	+ };
	2018	+ };
	2019	+ };
415	2020	};
416	2021
417	2022	prr: chipid@fff00044 {
..	..	@@ -420,6 +2025,37 @@
420	2025	};
421	2026	};
422	2027
	2028	+ thermal-zones {
	2029	+ cpu-thermal {
	2030	+ polling-delay-passive = <250>;
	2031	+ polling-delay = <0>;
	2032	+ thermal-sensors = <&thermal>;
	2033	+ sustainable-power = <717>;
	2034	+
	2035	+ cooling-maps {
	2036	+ map0 {
	2037	+ trip = <&target>;
	2038	+ cooling-device = <&a53_0 0 2>;
	2039	+ contribution = <1024>;
	2040	+ };
	2041	+ };
	2042	+
	2043	+ trips {
	2044	+ sensor1_crit: sensor1-crit {
	2045	+ temperature = <120000>;
	2046	+ hysteresis = <2000>;
	2047	+ type = "critical";
	2048	+ };
	2049	+
	2050	+ target: trip-point1 {
	2051	+ temperature = <100000>;
	2052	+ hysteresis = <2000>;
	2053	+ type = "passive";
	2054	+ };
	2055	+ };
	2056	+ };
	2057	+ };
	2058	+
423	2059	timer {
424	2060	compatible = "arm,armv8-timer";
425	2061	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,