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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
....@@ -1,4 +1,4 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
1
+// SPDX-License-Identifier: GPL-2.0
22 /*
33  * Device Tree Source for the ebisu board
44  *
....@@ -16,11 +16,92 @@
1616 	aliases {
1717 		serial0 = &scif2;
1818 		ethernet0 = &avb;
19
+		mmc0 = &sdhi3;
20
+		mmc1 = &sdhi0;
21
+		mmc2 = &sdhi1;
1922 	};
2023 
2124 	chosen {
22
-		bootargs = "ignore_loglevel";
25
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
2326 		stdout-path = "serial0:115200n8";
27
+	};
28
+
29
+	audio_clkout: audio-clkout {
30
+		/*
31
+		 * This is same as <&rcar_sound 0>
32
+		 * but needed to avoid cs2000/rcar_sound probe dead-lock
33
+		 */
34
+		compatible = "fixed-clock";
35
+		#clock-cells = <0>;
36
+		clock-frequency = <11289600>;
37
+	};
38
+
39
+	backlight: backlight {
40
+		compatible = "pwm-backlight";
41
+		pwms = <&pwm3 0 50000>;
42
+
43
+		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
44
+		default-brightness-level = <10>;
45
+
46
+		power-supply = <&reg_12p0v>;
47
+	};
48
+
49
+	cvbs-in {
50
+		compatible = "composite-video-connector";
51
+		label = "CVBS IN";
52
+
53
+		port {
54
+			cvbs_con: endpoint {
55
+				remote-endpoint = <&adv7482_ain7>;
56
+			};
57
+		};
58
+	};
59
+
60
+	hdmi-in {
61
+		compatible = "hdmi-connector";
62
+		label = "HDMI IN";
63
+		type = "a";
64
+
65
+		port {
66
+			hdmi_in_con: endpoint {
67
+				remote-endpoint = <&adv7482_hdmi>;
68
+			};
69
+		};
70
+	};
71
+
72
+	hdmi-out {
73
+		compatible = "hdmi-connector";
74
+		type = "a";
75
+
76
+		port {
77
+			hdmi_con_out: endpoint {
78
+				remote-endpoint = <&adv7511_out>;
79
+			};
80
+		};
81
+	};
82
+
83
+	lvds-decoder {
84
+		compatible = "thine,thc63lvd1024";
85
+		vcc-supply = <&reg_3p3v>;
86
+
87
+		ports {
88
+			#address-cells = <1>;
89
+			#size-cells = <0>;
90
+
91
+			port@0 {
92
+				reg = <0>;
93
+				thc63lvd1024_in: endpoint {
94
+					remote-endpoint = <&lvds0_out>;
95
+				};
96
+			};
97
+
98
+			port@2 {
99
+				reg = <2>;
100
+				thc63lvd1024_out: endpoint {
101
+					remote-endpoint = <&adv7511_in>;
102
+				};
103
+			};
104
+		};
24105 	};
25106 
26107 	memory@48000000 {
....@@ -28,13 +109,161 @@
28109 		/* first 128MB is reserved for secure area. */
29110 		reg = <0x0 0x48000000 0x0 0x38000000>;
30111 	};
112
+
113
+	reg_1p8v: regulator0 {
114
+		compatible = "regulator-fixed";
115
+		regulator-name = "fixed-1.8V";
116
+		regulator-min-microvolt = <1800000>;
117
+		regulator-max-microvolt = <1800000>;
118
+		regulator-boot-on;
119
+		regulator-always-on;
120
+	};
121
+
122
+	reg_3p3v: regulator1 {
123
+		compatible = "regulator-fixed";
124
+		regulator-name = "fixed-3.3V";
125
+		regulator-min-microvolt = <3300000>;
126
+		regulator-max-microvolt = <3300000>;
127
+		regulator-boot-on;
128
+		regulator-always-on;
129
+	};
130
+
131
+	reg_12p0v: regulator2 {
132
+		compatible = "regulator-fixed";
133
+		regulator-name = "D12.0V";
134
+		regulator-min-microvolt = <12000000>;
135
+		regulator-max-microvolt = <12000000>;
136
+		regulator-boot-on;
137
+		regulator-always-on;
138
+	};
139
+
140
+	rsnd_ak4613: sound {
141
+		compatible = "simple-audio-card";
142
+
143
+		simple-audio-card,name = "rsnd-ak4613";
144
+		simple-audio-card,format = "left_j";
145
+		simple-audio-card,bitclock-master = <&sndcpu>;
146
+		simple-audio-card,frame-master = <&sndcpu>;
147
+
148
+		sndcodec: simple-audio-card,codec {
149
+			sound-dai = <&ak4613>;
150
+		};
151
+
152
+		sndcpu: simple-audio-card,cpu {
153
+			sound-dai = <&rcar_sound>;
154
+		};
155
+	};
156
+
157
+	vbus0_usb2: regulator-vbus0-usb2 {
158
+		compatible = "regulator-fixed";
159
+
160
+		regulator-name = "USB20_VBUS_CN";
161
+		regulator-min-microvolt = <5000000>;
162
+		regulator-max-microvolt = <5000000>;
163
+
164
+		gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
165
+		enable-active-high;
166
+	};
167
+
168
+	vcc_sdhi0: regulator-vcc-sdhi0 {
169
+		compatible = "regulator-fixed";
170
+
171
+		regulator-name = "SDHI0 Vcc";
172
+		regulator-min-microvolt = <3300000>;
173
+		regulator-max-microvolt = <3300000>;
174
+
175
+		gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
176
+		enable-active-high;
177
+	};
178
+
179
+	vccq_sdhi0: regulator-vccq-sdhi0 {
180
+		compatible = "regulator-gpio";
181
+
182
+		regulator-name = "SDHI0 VccQ";
183
+		regulator-min-microvolt = <1800000>;
184
+		regulator-max-microvolt = <3300000>;
185
+
186
+		gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
187
+		gpios-states = <1>;
188
+		states = <3300000 1>, <1800000 0>;
189
+	};
190
+
191
+	vcc_sdhi1: regulator-vcc-sdhi1 {
192
+		compatible = "regulator-fixed";
193
+
194
+		regulator-name = "SDHI1 Vcc";
195
+		regulator-min-microvolt = <3300000>;
196
+		regulator-max-microvolt = <3300000>;
197
+
198
+		gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
199
+		enable-active-high;
200
+	};
201
+
202
+	vccq_sdhi1: regulator-vccq-sdhi1 {
203
+		compatible = "regulator-gpio";
204
+
205
+		regulator-name = "SDHI1 VccQ";
206
+		regulator-min-microvolt = <1800000>;
207
+		regulator-max-microvolt = <3300000>;
208
+
209
+		gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
210
+		gpios-states = <1>;
211
+		states = <3300000 1>, <1800000 0>;
212
+	};
213
+
214
+	vga {
215
+		compatible = "vga-connector";
216
+
217
+		port {
218
+			vga_in: endpoint {
219
+				remote-endpoint = <&adv7123_out>;
220
+			};
221
+		};
222
+	};
223
+
224
+	vga-encoder {
225
+		compatible = "adi,adv7123";
226
+
227
+		ports {
228
+			#address-cells = <1>;
229
+			#size-cells = <0>;
230
+
231
+			port@0 {
232
+				reg = <0>;
233
+				adv7123_in: endpoint {
234
+					remote-endpoint = <&du_out_rgb>;
235
+				};
236
+			};
237
+			port@1 {
238
+				reg = <1>;
239
+				adv7123_out: endpoint {
240
+					remote-endpoint = <&vga_in>;
241
+				};
242
+			};
243
+		};
244
+	};
245
+
246
+	x12_clk: x12 {
247
+		compatible = "fixed-clock";
248
+		#clock-cells = <0>;
249
+		clock-frequency = <24576000>;
250
+	};
251
+
252
+	x13_clk: x13 {
253
+		compatible = "fixed-clock";
254
+		#clock-cells = <0>;
255
+		clock-frequency = <74250000>;
256
+	};
257
+};
258
+
259
+&audio_clk_a {
260
+	clock-frequency = <22579200>;
31261 };
32262 
33263 &avb {
34264 	pinctrl-0 = <&avb_pins>;
35265 	pinctrl-names = "default";
36266 	phy-handle = <&phy0>;
37
-	phy-mode = "rgmii-txid";
38267 	status = "okay";
39268 
40269 	phy0: ethernet-phy@0 {
....@@ -43,10 +272,64 @@
43272 		interrupt-parent = <&gpio2>;
44273 		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
45274 		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
275
+		/*
276
+		 * TX clock internal delay mode is required for reliable
277
+		 * 1Gbps communication using the KSZ9031RNX phy present on
278
+		 * the Ebisu board, however, TX clock internal delay mode
279
+		 * isn't supported on r8a77990.  Thus, limit speed to
280
+		 * 100Mbps for reliable communication.
281
+		 */
282
+		max-speed = <100>;
283
+	};
284
+};
285
+
286
+&canfd {
287
+	pinctrl-0 = <&canfd0_pins>;
288
+	pinctrl-names = "default";
289
+	status = "okay";
290
+
291
+	channel0 {
292
+		status = "okay";
293
+	};
294
+};
295
+
296
+&csi40 {
297
+	status = "okay";
298
+
299
+	ports {
300
+		port@0 {
301
+			reg = <0>;
302
+
303
+			csi40_in: endpoint {
304
+				clock-lanes = <0>;
305
+				data-lanes = <1 2>;
306
+				remote-endpoint = <&adv7482_txa>;
307
+			};
308
+		};
309
+	};
310
+};
311
+
312
+&du {
313
+	pinctrl-0 = <&du_pins>;
314
+	pinctrl-names = "default";
315
+	status = "okay";
316
+
317
+	clocks = <&cpg CPG_MOD 724>,
318
+		 <&cpg CPG_MOD 723>,
319
+		 <&x13_clk>;
320
+	clock-names = "du.0", "du.1", "dclkin.0";
321
+
322
+	ports {
323
+		port@0 {
324
+			endpoint {
325
+				remote-endpoint = <&adv7123_in>;
326
+			};
327
+		};
46328 	};
47329 };
48330 
49331 &ehci0 {
332
+	dr_mode = "otg";
50333 	status = "okay";
51334 };
52335 
....@@ -54,20 +337,269 @@
54337 	clock-frequency = <48000000>;
55338 };
56339 
340
+&hsusb {
341
+	dr_mode = "otg";
342
+	status = "okay";
343
+};
344
+
345
+&i2c0 {
346
+	status = "okay";
347
+
348
+	io_expander: gpio@20 {
349
+		compatible = "onnn,pca9654";
350
+		reg = <0x20>;
351
+		gpio-controller;
352
+		#gpio-cells = <2>;
353
+		interrupt-parent = <&gpio2>;
354
+		interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
355
+	};
356
+
357
+	hdmi-encoder@39 {
358
+		compatible = "adi,adv7511w";
359
+		reg = <0x39>;
360
+		interrupt-parent = <&gpio1>;
361
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
362
+
363
+		adi,input-depth = <8>;
364
+		adi,input-colorspace = "rgb";
365
+		adi,input-clock = "1x";
366
+
367
+		ports {
368
+			#address-cells = <1>;
369
+			#size-cells = <0>;
370
+
371
+			port@0 {
372
+				reg = <0>;
373
+				adv7511_in: endpoint {
374
+					remote-endpoint = <&thc63lvd1024_out>;
375
+				};
376
+			};
377
+
378
+			port@1 {
379
+				reg = <1>;
380
+				adv7511_out: endpoint {
381
+					remote-endpoint = <&hdmi_con_out>;
382
+				};
383
+			};
384
+		};
385
+	};
386
+
387
+	video-receiver@70 {
388
+		compatible = "adi,adv7482";
389
+		reg = <0x70>;
390
+
391
+		#address-cells = <1>;
392
+		#size-cells = <0>;
393
+
394
+		interrupt-parent = <&gpio0>;
395
+		interrupt-names = "intrq1", "intrq2";
396
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
397
+			     <17 IRQ_TYPE_LEVEL_LOW>;
398
+
399
+		port@7 {
400
+			reg = <7>;
401
+
402
+			adv7482_ain7: endpoint {
403
+				remote-endpoint = <&cvbs_con>;
404
+			};
405
+		};
406
+
407
+		port@8 {
408
+			reg = <8>;
409
+
410
+			adv7482_hdmi: endpoint {
411
+				remote-endpoint = <&hdmi_in_con>;
412
+			};
413
+		};
414
+
415
+		port@a {
416
+			reg = <10>;
417
+
418
+			adv7482_txa: endpoint {
419
+				clock-lanes = <0>;
420
+				data-lanes = <1 2>;
421
+				remote-endpoint = <&csi40_in>;
422
+			};
423
+		};
424
+	};
425
+};
426
+
427
+&i2c3 {
428
+	status = "okay";
429
+
430
+	ak4613: codec@10 {
431
+		compatible = "asahi-kasei,ak4613";
432
+		#sound-dai-cells = <0>;
433
+		reg = <0x10>;
434
+		clocks = <&rcar_sound 3>;
435
+
436
+		asahi-kasei,in1-single-end;
437
+		asahi-kasei,in2-single-end;
438
+		asahi-kasei,out1-single-end;
439
+		asahi-kasei,out2-single-end;
440
+		asahi-kasei,out3-single-end;
441
+		asahi-kasei,out4-single-end;
442
+		asahi-kasei,out5-single-end;
443
+		asahi-kasei,out6-single-end;
444
+	};
445
+
446
+	cs2000: clk-multiplier@4f {
447
+		#clock-cells = <0>;
448
+		compatible = "cirrus,cs2000-cp";
449
+		reg = <0x4f>;
450
+		clocks = <&audio_clkout>, <&x12_clk>;
451
+		clock-names = "clk_in", "ref_clk";
452
+
453
+		assigned-clocks = <&cs2000>;
454
+		assigned-clock-rates = <24576000>; /* 1/1 divide */
455
+	};
456
+};
457
+
458
+&i2c_dvfs {
459
+	status = "okay";
460
+
461
+	clock-frequency = <400000>;
462
+
463
+	pmic: pmic@30 {
464
+		pinctrl-0 = <&irq0_pins>;
465
+		pinctrl-names = "default";
466
+
467
+		compatible = "rohm,bd9571mwv";
468
+		reg = <0x30>;
469
+		interrupt-parent = <&intc_ex>;
470
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
471
+		interrupt-controller;
472
+		#interrupt-cells = <2>;
473
+		gpio-controller;
474
+		#gpio-cells = <2>;
475
+		rohm,ddr-backup-power = <0x1>;
476
+		rohm,rstbmode-level;
477
+	};
478
+};
479
+
480
+&lvds0 {
481
+	status = "okay";
482
+
483
+	clocks = <&cpg CPG_MOD 727>,
484
+		 <&x13_clk>,
485
+		 <&extal_clk>;
486
+	clock-names = "fck", "dclkin.0", "extal";
487
+
488
+	ports {
489
+		port@1 {
490
+			lvds0_out: endpoint {
491
+				remote-endpoint = <&thc63lvd1024_in>;
492
+			};
493
+		};
494
+	};
495
+};
496
+
497
+&lvds1 {
498
+	/*
499
+	 * Even though the LVDS1 output is not connected, the encoder must be
500
+	 * enabled to supply a pixel clock to the DU for the DPAD output when
501
+	 * LVDS0 is in use.
502
+	 */
503
+	status = "okay";
504
+
505
+	clocks = <&cpg CPG_MOD 727>,
506
+		 <&x13_clk>,
507
+		 <&extal_clk>;
508
+	clock-names = "fck", "dclkin.0", "extal";
509
+};
510
+
57511 &ohci0 {
512
+	dr_mode = "otg";
513
+	status = "okay";
514
+};
515
+
516
+&pcie_bus_clk {
517
+	clock-frequency = <100000000>;
518
+};
519
+
520
+&pciec0 {
58521 	status = "okay";
59522 };
60523 
61524 &pfc {
62525 	avb_pins: avb {
63
-		mux {
64
-			groups = "avb_link", "avb_mii";
65
-			function = "avb";
66
-		};
526
+		groups = "avb_link", "avb_mii";
527
+		function = "avb";
528
+	};
529
+
530
+	canfd0_pins: canfd0 {
531
+		groups = "canfd0_data";
532
+		function = "canfd0";
533
+	};
534
+
535
+	du_pins: du {
536
+		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
537
+		function = "du";
538
+	};
539
+
540
+	irq0_pins: irq0 {
541
+		groups = "intc_ex_irq0";
542
+		function = "intc_ex";
543
+	};
544
+
545
+	pwm3_pins: pwm3 {
546
+		groups = "pwm3_b";
547
+		function = "pwm3";
548
+	};
549
+
550
+	pwm5_pins: pwm5 {
551
+		groups = "pwm5_a";
552
+		function = "pwm5";
553
+	};
554
+
555
+	scif2_pins: scif2 {
556
+		groups = "scif2_data_a";
557
+		function = "scif2";
558
+	};
559
+
560
+	sdhi0_pins: sd0 {
561
+		groups = "sdhi0_data4", "sdhi0_ctrl";
562
+		function = "sdhi0";
563
+		power-source = <3300>;
564
+	};
565
+
566
+	sdhi0_pins_uhs: sd0_uhs {
567
+		groups = "sdhi0_data4", "sdhi0_ctrl";
568
+		function = "sdhi0";
569
+		power-source = <1800>;
570
+	};
571
+
572
+	sdhi1_pins: sd1 {
573
+		groups = "sdhi1_data4", "sdhi1_ctrl";
574
+		function = "sdhi1";
575
+		power-source = <3300>;
576
+	};
577
+
578
+	sdhi1_pins_uhs: sd1_uhs {
579
+		groups = "sdhi1_data4", "sdhi1_ctrl";
580
+		function = "sdhi1";
581
+		power-source = <1800>;
582
+	};
583
+
584
+	sdhi3_pins: sd3 {
585
+		groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
586
+		function = "sdhi3";
587
+		power-source = <1800>;
588
+	};
589
+
590
+	sound_clk_pins: sound_clk {
591
+		groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
592
+			 "audio_clkout_a", "audio_clkout1_a";
593
+		function = "audio_clk";
594
+	};
595
+
596
+	sound_pins: sound {
597
+		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
598
+		function = "ssi";
67599 	};
68600 
69601 	usb0_pins: usb {
70
-		groups = "usb0_b";
602
+		groups = "usb0_b", "usb0_id";
71603 		function = "usb0";
72604 	};
73605 
....@@ -77,19 +609,139 @@
77609 	};
78610 };
79611 
612
+&pwm3 {
613
+	pinctrl-0 = <&pwm3_pins>;
614
+	pinctrl-names = "default";
615
+
616
+	status = "okay";
617
+};
618
+
619
+&pwm5 {
620
+	pinctrl-0 = <&pwm5_pins>;
621
+	pinctrl-names = "default";
622
+
623
+	status = "okay";
624
+};
625
+
626
+&rcar_sound {
627
+	pinctrl-0 = <&sound_pins &sound_clk_pins>;
628
+	pinctrl-names = "default";
629
+
630
+	/* Single DAI */
631
+	#sound-dai-cells = <0>;
632
+
633
+	/* audio_clkout0/1/2/3 */
634
+	#clock-cells = <1>;
635
+	clock-frequency = <12288000 11289600>;
636
+
637
+	status = "okay";
638
+
639
+	/* update <audio_clk_b> to <cs2000> */
640
+	clocks = <&cpg CPG_MOD 1005>,
641
+		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
642
+		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
643
+		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
644
+		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
645
+		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
646
+		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
647
+		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
648
+		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
649
+		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
650
+		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
651
+		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
652
+		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
653
+		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
654
+		 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
655
+		 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
656
+
657
+	rcar_sound,dai {
658
+		dai0 {
659
+			playback = <&ssi0 &src0 &dvc0>;
660
+			capture  = <&ssi1 &src1 &dvc1>;
661
+		};
662
+	};
663
+
664
+};
665
+
80666 &rwdt {
81667 	timeout-sec = <60>;
82668 	status = "okay";
83669 };
84670 
85671 &scif2 {
672
+	pinctrl-0 = <&scif2_pins>;
673
+	pinctrl-names = "default";
674
+
86675 	status = "okay";
676
+};
677
+
678
+&sdhi0 {
679
+	pinctrl-0 = <&sdhi0_pins>;
680
+	pinctrl-1 = <&sdhi0_pins_uhs>;
681
+	pinctrl-names = "default", "state_uhs";
682
+
683
+	vmmc-supply = <&vcc_sdhi0>;
684
+	vqmmc-supply = <&vccq_sdhi0>;
685
+	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
686
+	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
687
+	bus-width = <4>;
688
+	sd-uhs-sdr50;
689
+	sd-uhs-sdr104;
690
+	status = "okay";
691
+};
692
+
693
+&sdhi1 {
694
+	pinctrl-0 = <&sdhi1_pins>;
695
+	pinctrl-1 = <&sdhi1_pins_uhs>;
696
+	pinctrl-names = "default", "state_uhs";
697
+
698
+	vmmc-supply = <&vcc_sdhi1>;
699
+	vqmmc-supply = <&vccq_sdhi1>;
700
+	cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
701
+	bus-width = <4>;
702
+	sd-uhs-sdr50;
703
+	sd-uhs-sdr104;
704
+	status = "okay";
705
+};
706
+
707
+&sdhi3 {
708
+	/* used for on-board 8bit eMMC */
709
+	pinctrl-0 = <&sdhi3_pins>;
710
+	pinctrl-1 = <&sdhi3_pins>;
711
+	pinctrl-names = "default", "state_uhs";
712
+
713
+	vmmc-supply = <&reg_3p3v>;
714
+	vqmmc-supply = <&reg_1p8v>;
715
+	mmc-hs200-1_8v;
716
+	mmc-hs400-1_8v;
717
+	bus-width = <8>;
718
+	non-removable;
719
+	full-pwr-cycle-in-suspend;
720
+	status = "okay";
721
+};
722
+
723
+&ssi1 {
724
+	shared-pin;
87725 };
88726 
89727 &usb2_phy0 {
90728 	pinctrl-0 = <&usb0_pins>;
91729 	pinctrl-names = "default";
92730 
731
+	vbus-supply = <&vbus0_usb2>;
732
+	status = "okay";
733
+};
734
+
735
+&usb3_peri0 {
736
+	companion = <&xhci0>;
737
+	status = "okay";
738
+};
739
+
740
+&vin4 {
741
+	status = "okay";
742
+};
743
+
744
+&vin5 {
93745 	status = "okay";
94746 };
95747