| .. | .. |
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| 21 | 21 | stdout-path = "serial0:115200n8"; |
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| 22 | 22 | }; |
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| 23 | 23 | |
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| 24 | + hdmi-out { |
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| 25 | + compatible = "hdmi-connector"; |
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| 26 | + type = "a"; |
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| 27 | + |
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| 28 | + port { |
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| 29 | + hdmi_con: endpoint { |
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| 30 | + remote-endpoint = <&adv7511_out>; |
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| 31 | + }; |
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| 32 | + }; |
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| 33 | + }; |
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| 34 | + |
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| 35 | + lvds-decoder { |
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| 36 | + compatible = "thine,thc63lvd1024"; |
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| 37 | + vcc-supply = <&vcc_d3_3v>; |
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| 38 | + |
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| 39 | + ports { |
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| 40 | + #address-cells = <1>; |
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| 41 | + #size-cells = <0>; |
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| 42 | + |
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| 43 | + port@0 { |
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| 44 | + reg = <0>; |
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| 45 | + thc63lvd1024_in: endpoint { |
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| 46 | + remote-endpoint = <&lvds0_out>; |
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| 47 | + }; |
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| 48 | + }; |
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| 49 | + |
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| 50 | + port@2 { |
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| 51 | + reg = <2>; |
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| 52 | + thc63lvd1024_out: endpoint { |
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| 53 | + remote-endpoint = <&adv7511_in>; |
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| 54 | + }; |
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| 55 | + }; |
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| 56 | + }; |
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| 57 | + }; |
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| 58 | + |
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| 24 | 59 | memory@48000000 { |
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| 25 | 60 | device_type = "memory"; |
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| 26 | 61 | /* first 128MB is reserved for secure area. */ |
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| .. | .. |
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| 51 | 86 | regulator-always-on; |
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| 52 | 87 | }; |
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| 53 | 88 | |
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| 54 | | - lvds-decoder { |
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| 55 | | - compatible = "thine,thc63lvd1024"; |
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| 56 | | - vcc-supply = <&vcc_d3_3v>; |
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| 57 | | - |
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| 58 | | - ports { |
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| 59 | | - #address-cells = <1>; |
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| 60 | | - #size-cells = <0>; |
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| 61 | | - |
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| 62 | | - port@0 { |
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| 63 | | - reg = <0>; |
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| 64 | | - thc63lvd1024_in: endpoint { |
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| 65 | | - remote-endpoint = <&lvds0_out>; |
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| 66 | | - }; |
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| 67 | | - }; |
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| 68 | | - |
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| 69 | | - port@2 { |
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| 70 | | - reg = <2>; |
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| 71 | | - thc63lvd1024_out: endpoint { |
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| 72 | | - remote-endpoint = <&adv7511_in>; |
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| 73 | | - }; |
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| 74 | | - }; |
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| 75 | | - }; |
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| 76 | | - }; |
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| 77 | | - |
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| 78 | | - hdmi-out { |
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| 79 | | - compatible = "hdmi-connector"; |
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| 80 | | - type = "a"; |
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| 81 | | - |
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| 82 | | - port { |
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| 83 | | - hdmi_con: endpoint { |
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| 84 | | - remote-endpoint = <&adv7511_out>; |
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| 85 | | - }; |
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| 86 | | - }; |
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| 89 | + vcc_vddq_vin0: regulator-2 { |
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| 90 | + compatible = "regulator-fixed"; |
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| 91 | + regulator-name = "VCC_VDDQ_VIN0"; |
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| 92 | + regulator-min-microvolt = <3300000>; |
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| 93 | + regulator-max-microvolt = <3300000>; |
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| 94 | + regulator-boot-on; |
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| 95 | + regulator-always-on; |
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| 87 | 96 | }; |
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| 88 | 97 | }; |
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| 89 | 98 | |
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| .. | .. |
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| 99 | 108 | phy0: ethernet-phy@0 { |
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| 100 | 109 | rxc-skew-ps = <1500>; |
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| 101 | 110 | reg = <0>; |
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| 111 | + interrupt-parent = <&gpio1>; |
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| 112 | + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; |
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| 102 | 113 | }; |
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| 103 | 114 | }; |
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| 104 | 115 | |
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| .. | .. |
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| 115 | 126 | |
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| 116 | 127 | &extalr_clk { |
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| 117 | 128 | clock-frequency = <32768>; |
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| 118 | | -}; |
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| 119 | | - |
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| 120 | | -&pfc { |
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| 121 | | - avb_pins: avb0 { |
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| 122 | | - groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; |
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| 123 | | - function = "avb0"; |
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| 124 | | - }; |
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| 125 | | - |
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| 126 | | - i2c0_pins: i2c0 { |
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| 127 | | - groups = "i2c0"; |
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| 128 | | - function = "i2c0"; |
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| 129 | | - }; |
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| 130 | | - |
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| 131 | | - scif0_pins: scif0 { |
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| 132 | | - groups = "scif0_data"; |
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| 133 | | - function = "scif0"; |
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| 134 | | - }; |
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| 135 | 129 | }; |
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| 136 | 130 | |
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| 137 | 131 | &i2c0 { |
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| .. | .. |
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| 156 | 150 | adi,input-depth = <8>; |
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| 157 | 151 | adi,input-colorspace = "rgb"; |
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| 158 | 152 | adi,input-clock = "1x"; |
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| 159 | | - adi,input-style = <1>; |
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| 160 | | - adi,input-justification = "evenly"; |
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| 161 | 153 | |
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| 162 | 154 | ports { |
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| 163 | 155 | #address-cells = <1>; |
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| .. | .. |
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| 192 | 184 | }; |
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| 193 | 185 | }; |
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| 194 | 186 | |
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| 187 | +&mmc0 { |
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| 188 | + pinctrl-0 = <&mmc_pins>; |
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| 189 | + pinctrl-names = "default"; |
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| 190 | + |
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| 191 | + vmmc-supply = <&vcc_d3_3v>; |
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| 192 | + vqmmc-supply = <&vcc_vddq_vin0>; |
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| 193 | + bus-width = <8>; |
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| 194 | + non-removable; |
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| 195 | + status = "okay"; |
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| 196 | +}; |
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| 197 | + |
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| 198 | +&pfc { |
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| 199 | + avb_pins: avb0 { |
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| 200 | + groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; |
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| 201 | + function = "avb0"; |
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| 202 | + }; |
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| 203 | + |
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| 204 | + i2c0_pins: i2c0 { |
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| 205 | + groups = "i2c0"; |
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| 206 | + function = "i2c0"; |
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| 207 | + }; |
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| 208 | + |
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| 209 | + mmc_pins: mmc_3_3v { |
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| 210 | + groups = "mmc_data8", "mmc_ctrl"; |
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| 211 | + function = "mmc"; |
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| 212 | + power-source = <3300>; |
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| 213 | + }; |
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| 214 | + |
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| 215 | + qspi0_pins: qspi0 { |
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| 216 | + groups = "qspi0_ctrl", "qspi0_data4"; |
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| 217 | + function = "qspi0"; |
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| 218 | + }; |
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| 219 | + |
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| 220 | + scif0_pins: scif0 { |
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| 221 | + groups = "scif0_data"; |
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| 222 | + function = "scif0"; |
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| 223 | + }; |
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| 224 | +}; |
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| 225 | + |
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| 226 | +&rpc { |
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| 227 | + pinctrl-0 = <&qspi0_pins>; |
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| 228 | + pinctrl-names = "default"; |
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| 229 | + |
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| 230 | + status = "okay"; |
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| 231 | + |
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| 232 | + flash@0 { |
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| 233 | + compatible = "spansion,s25fs512s", "jedec,spi-nor"; |
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| 234 | + reg = <0>; |
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| 235 | + spi-max-frequency = <50000000>; |
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| 236 | + spi-rx-bus-width = <4>; |
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| 237 | + |
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| 238 | + partitions { |
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| 239 | + compatible = "fixed-partitions"; |
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| 240 | + #address-cells = <1>; |
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| 241 | + #size-cells = <1>; |
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| 242 | + |
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| 243 | + bootparam@0 { |
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| 244 | + reg = <0x00000000 0x040000>; |
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| 245 | + read-only; |
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| 246 | + }; |
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| 247 | + cr7@40000 { |
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| 248 | + reg = <0x00040000 0x080000>; |
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| 249 | + read-only; |
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| 250 | + }; |
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| 251 | + cert_header_sa3@c0000 { |
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| 252 | + reg = <0x000c0000 0x080000>; |
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| 253 | + read-only; |
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| 254 | + }; |
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| 255 | + bl2@140000 { |
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| 256 | + reg = <0x00140000 0x040000>; |
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| 257 | + read-only; |
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| 258 | + }; |
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| 259 | + cert_header_sa6@180000 { |
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| 260 | + reg = <0x00180000 0x040000>; |
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| 261 | + read-only; |
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| 262 | + }; |
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| 263 | + bl31@1c0000 { |
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| 264 | + reg = <0x001c0000 0x460000>; |
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| 265 | + read-only; |
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| 266 | + }; |
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| 267 | + uboot@640000 { |
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| 268 | + reg = <0x00640000 0x0c0000>; |
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| 269 | + read-only; |
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| 270 | + }; |
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| 271 | + uboot-env@700000 { |
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| 272 | + reg = <0x00700000 0x040000>; |
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| 273 | + read-only; |
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| 274 | + }; |
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| 275 | + dtb@740000 { |
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| 276 | + reg = <0x00740000 0x080000>; |
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| 277 | + }; |
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| 278 | + kernel@7c0000 { |
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| 279 | + reg = <0x007c0000 0x1400000>; |
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| 280 | + }; |
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| 281 | + user@1bc0000 { |
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| 282 | + reg = <0x01bc0000 0x2440000>; |
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| 283 | + }; |
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| 284 | + }; |
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| 285 | + }; |
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| 286 | +}; |
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| 287 | + |
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| 195 | 288 | &scif0 { |
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| 196 | 289 | pinctrl-0 = <&scif0_pins>; |
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| 197 | 290 | pinctrl-names = "default"; |
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