kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm64/boot/dts/realtek/rtd129x.dtsi
..
..
@@ -1,61 +1,112 @@
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+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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 /*
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  * Realtek RTD1293/RTD1295/RTD1296 SoC
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  *
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- * Copyright (c) 2016-2017 Andreas Färber
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- *
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- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+ * Copyright (c) 2016-2019 Andreas Färber
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  */
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-/memreserve/	0x0000000000000000 0x0000000000030000;
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-/memreserve/	0x000000000001f000 0x0000000000001000;
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-/memreserve/	0x0000000000030000 0x00000000000d0000;
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+/memreserve/	0x0000000000000000 0x000000000001f000;
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+/memreserve/	0x000000000001f000 0x00000000000e1000;
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 /memreserve/	0x0000000001b00000 0x00000000004be000;
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-/memreserve/	0x0000000001ffe000 0x0000000000004000;
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11
 
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/reset/realtek,rtd1295.h>
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14
 
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 / {
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 	interrupt-parent = <&gic>;
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 	#address-cells = <1>;
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 	#size-cells = <1>;
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19
 
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+	reserved-memory {
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+		#address-cells = <1>;
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+		#size-cells = <1>;
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+		ranges;
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+
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+		rpc_comm: rpc@1f000 {
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+			reg = <0x1f000 0x1000>;
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+		};
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+
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+		rpc_ringbuf: rpc@1ffe000 {
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+			reg = <0x1ffe000 0x4000>;
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+		};
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+
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+		tee: tee@10100000 {
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+			reg = <0x10100000 0xf00000>;
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+			no-map;
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+		};
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+	};
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+
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 	arm_pmu: arm-pmu {
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 		compatible = "arm,cortex-a53-pmu";
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 		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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+	};
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+
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+	osc27M: osc {
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+		compatible = "fixed-clock";
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+		clock-frequency = <27000000>;
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+		#clock-cells = <0>;
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+		clock-output-names = "osc27M";
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 	};
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50
 
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 	soc {
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 		compatible = "simple-bus";
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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-		/* Exclude up to 2 GiB of RAM */
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-		ranges = <0x80000000 0x80000000 0x80000000>;
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+		ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
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+			 /* Exclude up to 2 GiB of RAM */
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+			 <0x80000000 0x80000000 0x80000000>;
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58
 
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-		uart0: serial@98007800 {
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-			compatible = "snps,dw-apb-uart";
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-			reg = <0x98007800 0x400>;
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-			reg-shift = <2>;
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-			reg-io-width = <4>;
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-			clock-frequency = <27000000>;
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-			status = "disabled";
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-		};
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+		rbus: bus@98000000 {
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+			compatible = "simple-bus";
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+			reg = <0x98000000 0x200000>;
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x98000000 0x200000>;
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-		uart1: serial@9801b200 {
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-			compatible = "snps,dw-apb-uart";
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-			reg = <0x9801b200 0x100>;
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-			reg-shift = <2>;
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-			reg-io-width = <4>;
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-			clock-frequency = <432000000>;
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-			status = "disabled";
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-		};
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+			crt: syscon@0 {
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+				compatible = "syscon", "simple-mfd";
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+				reg = <0x0 0x1800>;
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+				reg-io-width = <4>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				ranges = <0x0 0x0 0x1800>;
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+			};
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-		uart2: serial@9801b400 {
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-			compatible = "snps,dw-apb-uart";
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-			reg = <0x9801b400 0x100>;
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-			reg-shift = <2>;
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-			reg-io-width = <4>;
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-			clock-frequency = <432000000>;
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-			status = "disabled";
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+			iso: syscon@7000 {
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+				compatible = "syscon", "simple-mfd";
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+				reg = <0x7000 0x1000>;
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+				reg-io-width = <4>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				ranges = <0x0 0x7000 0x1000>;
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+			};
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+
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+			sb2: syscon@1a000 {
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+				compatible = "syscon", "simple-mfd";
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+				reg = <0x1a000 0x1000>;
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+				reg-io-width = <4>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				ranges = <0x0 0x1a000 0x1000>;
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+			};
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+
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+			misc: syscon@1b000 {
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+				compatible = "syscon", "simple-mfd";
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+				reg = <0x1b000 0x1000>;
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+				reg-io-width = <4>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				ranges = <0x0 0x1b000 0x1000>;
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+			};
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+
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+			scpu_wrapper: syscon@1d000 {
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+				compatible = "syscon", "simple-mfd";
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+				reg = <0x1d000 0x2000>;
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+				reg-io-width = <4>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				ranges = <0x0 0x1d000 0x2000>;
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+			};
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 		};
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111
 
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 		gic: interrupt-controller@ff011000 {
..
..
@@ -70,3 +121,75 @@
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 		};
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 	};
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 };
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+
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+&crt {
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+	reset1: reset-controller@0 {
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+		compatible = "snps,dw-low-reset";
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+		reg = <0x0 0x4>;
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+		#reset-cells = <1>;
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+	};
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+
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+	reset2: reset-controller@4 {
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+		compatible = "snps,dw-low-reset";
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+		reg = <0x4 0x4>;
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+		#reset-cells = <1>;
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+	};
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+
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+	reset3: reset-controller@8 {
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+		compatible = "snps,dw-low-reset";
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+		reg = <0x8 0x4>;
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+		#reset-cells = <1>;
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+	};
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+
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+	reset4: reset-controller@50 {
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+		compatible = "snps,dw-low-reset";
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+		reg = <0x50 0x4>;
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+		#reset-cells = <1>;
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+	};
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+};
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+
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+&iso {
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+	iso_reset: reset-controller@88 {
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+		compatible = "snps,dw-low-reset";
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+		reg = <0x88 0x4>;
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+		#reset-cells = <1>;
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+	};
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+
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+	wdt: watchdog@680 {
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+		compatible = "realtek,rtd1295-watchdog";
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+		reg = <0x680 0x100>;
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+		clocks = <&osc27M>;
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+	};
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+
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+	uart0: serial@800 {
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+		compatible = "snps,dw-apb-uart";
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+		reg = <0x800 0x400>;
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+		reg-shift = <2>;
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+		reg-io-width = <4>;
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+		clock-frequency = <27000000>;
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+		resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
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+		status = "disabled";
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+	};
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+};
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+
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+&misc {
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+	uart1: serial@200 {
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+		compatible = "snps,dw-apb-uart";
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+		reg = <0x200 0x100>;
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+		reg-shift = <2>;
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+		reg-io-width = <4>;
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+		clock-frequency = <432000000>;
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+		resets = <&reset2 RTD1295_RSTN_UR1>;
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+		status = "disabled";
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+	};
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+
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+	uart2: serial@400 {
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+		compatible = "snps,dw-apb-uart";
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+		reg = <0x400 0x100>;
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+		reg-shift = <2>;
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+		reg-io-width = <4>;
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+		clock-frequency = <432000000>;
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+		resets = <&reset2 RTD1295_RSTN_UR2>;
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+		status = "disabled";
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+	};
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+};