forked from ~ljy/RK356X_SDK_RELEASE

hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f
kernel/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
....@@ -17,23 +17,23 @@
1717 /*
1818 * Instantiate the CP110
1919 */
20
-#define CP110_NAME cp0
21
-#define CP110_BASE f2000000
22
-#define CP110_PCIE_IO_BASE 0xf9000000
23
-#define CP110_PCIE_MEM_BASE 0xf6000000
24
-#define CP110_PCIE0_BASE f2600000
25
-#define CP110_PCIE1_BASE f2620000
26
-#define CP110_PCIE2_BASE f2640000
20
+#define CP11X_NAME cp0
21
+#define CP11X_BASE f2000000
22
+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
23
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
24
+#define CP11X_PCIE0_BASE f2600000
25
+#define CP11X_PCIE1_BASE f2620000
26
+#define CP11X_PCIE2_BASE f2640000
2727
2828 #include "armada-cp110.dtsi"
2929
30
-#undef CP110_NAME
31
-#undef CP110_BASE
32
-#undef CP110_PCIE_IO_BASE
33
-#undef CP110_PCIE_MEM_BASE
34
-#undef CP110_PCIE0_BASE
35
-#undef CP110_PCIE1_BASE
36
-#undef CP110_PCIE2_BASE
30
+#undef CP11X_NAME
31
+#undef CP11X_BASE
32
+#undef CP11X_PCIEx_MEM_BASE
33
+#undef CP11X_PCIEx_MEM_SIZE
34
+#undef CP11X_PCIE0_BASE
35
+#undef CP11X_PCIE1_BASE
36
+#undef CP11X_PCIE2_BASE
3737
3838 &cp0_gpio1 {
3939 status = "okay";