kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm64/boot/dts/lg/lg1312.dtsi
..
..
@@ -21,27 +21,27 @@
21
21
 
22
22
 		cpu0: cpu@0 {
23
23
 			device_type = "cpu";
24
-			compatible = "arm,cortex-a53", "arm,armv8";
24
+			compatible = "arm,cortex-a53";
25
25
 			reg = <0x0 0x0>;
26
26
 			next-level-cache = <&L2_0>;
27
27
 		};
28
28
 		cpu1: cpu@1 {
29
29
 			device_type = "cpu";
30
-			compatible = "arm,cortex-a53", "arm,armv8";
30
+			compatible = "arm,cortex-a53";
31
31
 			reg = <0x0 0x1>;
32
32
 			enable-method = "psci";
33
33
 			next-level-cache = <&L2_0>;
34
34
 		};
35
35
 		cpu2: cpu@2 {
36
36
 			device_type = "cpu";
37
-			compatible = "arm,cortex-a53", "arm,armv8";
37
+			compatible = "arm,cortex-a53";
38
38
 			reg = <0x0 0x2>;
39
39
 			enable-method = "psci";
40
40
 			next-level-cache = <&L2_0>;
41
41
 		};
42
42
 		cpu3: cpu@3 {
43
43
 			device_type = "cpu";
44
-			compatible = "arm,cortex-a53", "arm,armv8";
44
+			compatible = "arm,cortex-a53";
45
45
 			reg = <0x0 0x3>;
46
46
 			enable-method = "psci";
47
47
 			next-level-cache = <&L2_0>;
..
..
@@ -124,25 +124,25 @@
124
124
 	amba {
125
125
 		#address-cells = <2>;
126
126
 		#size-cells = <1>;
127
-		#interrupts-cells = <3>;
127
+		#interrupt-cells = <3>;
128
128
 
129
129
 		compatible = "simple-bus";
130
130
 		interrupt-parent = <&gic>;
131
131
 		ranges;
132
132
 
133
133
 		timers: timer@fd100000 {
134
-			compatible = "arm,sp804";
134
+			compatible = "arm,sp804", "arm,primecell";
135
135
 			reg = <0x0 0xfd100000 0x1000>;
136
136
 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
137
-			clocks = <&clk_bus>;
138
-			clock-names = "apb_pclk";
137
+			clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
138
+			clock-names = "timer0clk", "timer1clk", "apb_pclk";
139
139
 		};
140
140
 		wdog: watchdog@fd200000 {
141
141
 			compatible = "arm,sp805", "arm,primecell";
142
142
 			reg = <0x0 0xfd200000 0x1000>;
143
143
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
144
-			clocks = <&clk_bus>;
145
-			clock-names = "apb_pclk";
144
+			clocks = <&clk_bus>, <&clk_bus>;
145
+			clock-names = "wdog_clk", "apb_pclk";
146
146
 		};
147
147
 		uart0: serial@fe000000 {
148
148
 			compatible = "arm,pl011", "arm,primecell";