kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
..
..
@@ -56,7 +56,7 @@
56
56
 		};
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57
 
58
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 		cpu0: cpu@0 {
59
-			compatible = "arm,cortex-a53", "arm,armv8";
59
+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x0>;
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62
 			enable-method = "psci";
..
..
@@ -70,7 +70,7 @@
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 		};
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 		cpu1: cpu@1 {
73
-			compatible = "arm,cortex-a53", "arm,armv8";
73
+			compatible = "arm,cortex-a53";
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 			device_type = "cpu";
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 			reg = <0x0 0x1>;
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 			enable-method = "psci";
..
..
@@ -79,10 +79,11 @@
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 			capacity-dmips-mhz = <592>;
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 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
81
81
 			operating-points-v2 = <&cluster0_opp>;
82
+			#cooling-cells = <2>;
82
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 		};
83
84
 
84
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 		cpu2: cpu@2 {
85
-			compatible = "arm,cortex-a53", "arm,armv8";
86
+			compatible = "arm,cortex-a53";
86
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 			device_type = "cpu";
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 			reg = <0x0 0x2>;
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 			enable-method = "psci";
..
..
@@ -91,10 +92,11 @@
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 			capacity-dmips-mhz = <592>;
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 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
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 			operating-points-v2 = <&cluster0_opp>;
95
+			#cooling-cells = <2>;
94
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 		};
95
97
 
96
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 		cpu3: cpu@3 {
97
-			compatible = "arm,cortex-a53", "arm,armv8";
99
+			compatible = "arm,cortex-a53";
98
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 			device_type = "cpu";
99
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 			reg = <0x0 0x3>;
100
102
 			enable-method = "psci";
..
..
@@ -103,10 +105,11 @@
103
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 			capacity-dmips-mhz = <592>;
104
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 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
105
107
 			operating-points-v2 = <&cluster0_opp>;
108
+			#cooling-cells = <2>;
106
109
 		};
107
110
 
108
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 		cpu4: cpu@100 {
109
-			compatible = "arm,cortex-a73", "arm,armv8";
112
+			compatible = "arm,cortex-a73";
110
113
 			device_type = "cpu";
111
114
 			reg = <0x0 0x100>;
112
115
 			enable-method = "psci";
..
..
@@ -120,7 +123,7 @@
120
123
 		};
121
124
 
122
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 		cpu5: cpu@101 {
123
-			compatible = "arm,cortex-a73", "arm,armv8";
126
+			compatible = "arm,cortex-a73";
124
127
 			device_type = "cpu";
125
128
 			reg = <0x0 0x101>;
126
129
 			enable-method = "psci";
..
..
@@ -129,10 +132,11 @@
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 			capacity-dmips-mhz = <1024>;
130
133
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
131
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 			operating-points-v2 = <&cluster1_opp>;
135
+			#cooling-cells = <2>;
132
136
 		};
133
137
 
134
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 		cpu6: cpu@102 {
135
-			compatible = "arm,cortex-a73", "arm,armv8";
139
+			compatible = "arm,cortex-a73";
136
140
 			device_type = "cpu";
137
141
 			reg = <0x0 0x102>;
138
142
 			enable-method = "psci";
..
..
@@ -141,10 +145,11 @@
141
145
 			capacity-dmips-mhz = <1024>;
142
146
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
143
147
 			operating-points-v2 = <&cluster1_opp>;
148
+			#cooling-cells = <2>;
144
149
 		};
145
150
 
146
151
 		cpu7: cpu@103 {
147
-			compatible = "arm,cortex-a73", "arm,armv8";
152
+			compatible = "arm,cortex-a73";
148
153
 			device_type = "cpu";
149
154
 			reg = <0x0 0x103>;
150
155
 			enable-method = "psci";
..
..
@@ -153,6 +158,7 @@
153
158
 			capacity-dmips-mhz = <1024>;
154
159
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
155
160
 			operating-points-v2 = <&cluster1_opp>;
161
+			#cooling-cells = <2>;
156
162
 		};
157
163
 
158
164
 		idle-states {
..
..
@@ -425,7 +431,7 @@
425
431
 			resets = <&iomcu_rst 0x20 4>;
426
432
 			pinctrl-names = "default";
427
433
 			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
428
-			status = "disabled";
434
+			status = "ok";
429
435
 		};
430
436
 
431
437
 		i2c3: i2c@fdf0c000 {
..
..
@@ -472,6 +478,8 @@
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 			compatible = "arm,pl011", "arm,primecell";
473
479
 			reg = <0x0 0xfdf00000 0x0 0x1000>;
474
480
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
481
+			dma-names = "rx", "tx";
482
+			dmas =  <&dma0 2 &dma0 3>;
475
483
 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
476
484
 				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
477
485
 			clock-names = "uartclk", "apb_pclk";
..
..
@@ -484,6 +492,8 @@
484
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 			compatible = "arm,pl011", "arm,primecell";
485
493
 			reg = <0x0 0xfdf03000 0x0 0x1000>;
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 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
495
+			dma-names = "rx", "tx";
496
+			dmas =  <&dma0 4 &dma0 5>;
487
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 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
488
498
 				 <&crg_ctrl HI3660_PCLK>;
489
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 			clock-names = "uartclk", "apb_pclk";
..
..
@@ -508,6 +518,8 @@
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 			compatible = "arm,pl011", "arm,primecell";
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 			reg = <0x0 0xfdf01000 0x0 0x1000>;
510
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 			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
521
+			dma-names = "rx", "tx";
522
+			dmas =  <&dma0 6 &dma0 7>;
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 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
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 				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
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525
 			clock-names = "uartclk", "apb_pclk";
..
..
@@ -520,6 +532,8 @@
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532
 			compatible = "arm,pl011", "arm,primecell";
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 			reg = <0x0 0xfdf05000 0x0 0x1000>;
522
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 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
535
+			dma-names = "rx", "tx";
536
+			dmas =  <&dma0 8 &dma0 9>;
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 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
524
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 				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
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539
 			clock-names = "uartclk", "apb_pclk";
..
..
@@ -546,11 +560,21 @@
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 			#dma-cells = <1>;
547
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 			dma-channels = <16>;
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 			dma-requests = <32>;
549
-			dma-min-chan = <1>;
563
+			dma-channel-mask = <0xfffe>;
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 			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
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 			dma-no-cci;
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 			dma-type = "hi3660_dma";
568
+		};
569
+
570
+		asp_dmac: dma-controller@e804b000 {
571
+			compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
572
+			reg = <0x0 0xe804b000 0x0 0x1000>;
573
+			#dma-cells = <1>;
574
+			dma-channels = <16>;
575
+			dma-requests = <32>;
576
+			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
577
+			interrupt-names = "asp_dma_irq";
554
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 		};
555
579
 
556
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 		rtc0: rtc@fff04000 {
..
..
@@ -950,7 +974,7 @@
950
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 			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
951
975
 			clock-names = "apb_pclk";
952
976
 			pinctrl-names = "default";
953
-			pinctrl-0 = <&spi2_pmx_func>;
977
+			pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
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 			num-cs = <1>;
955
979
 			cs-gpios = <&gpio27 2 0>;
956
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 			status = "disabled";
..
..
@@ -965,7 +989,7 @@
965
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 			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
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 			clock-names = "apb_pclk";
967
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 			pinctrl-names = "default";
968
-			pinctrl-0 = <&spi3_pmx_func>;
992
+			pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
969
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 			num-cs = <1>;
970
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 			cs-gpios = <&gpio18 5 0>;
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 			status = "disabled";
..
..
@@ -1065,16 +1089,18 @@
1065
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 			compatible = "arm,sp805", "arm,primecell";
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 			reg = <0x0 0xe8a06000 0x0 0x1000>;
1067
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 			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1068
-			clocks = <&crg_ctrl HI3660_OSC32K>;
1069
-			clock-names = "apb_pclk";
1092
+			clocks = <&crg_ctrl HI3660_OSC32K>,
1093
+				 <&crg_ctrl HI3660_OSC32K>;
1094
+			clock-names = "wdog_clk", "apb_pclk";
1070
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 		};
1071
1096
 
1072
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 		watchdog1: watchdog@e8a07000 {
1073
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 			compatible = "arm,sp805", "arm,primecell";
1074
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 			reg = <0x0 0xe8a07000 0x0 0x1000>;
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 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1076
-			clocks = <&crg_ctrl HI3660_OSC32K>;
1077
-			clock-names = "apb_pclk";
1101
+			clocks = <&crg_ctrl HI3660_OSC32K>,
1102
+				 <&crg_ctrl HI3660_OSC32K>;
1103
+			clock-names = "wdog_clk", "apb_pclk";
1078
1104
 		};
1079
1105
 
1080
1106
 		tsensor: tsensor@fff30000 {
..
..
@@ -1112,15 +1138,57 @@
1112
1138
 					map0 {
1113
1139
 						trip = <&target>;
1114
1140
 						contribution = <1024>;
1115
-						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1141
+						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1142
+								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1143
+								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1144
+								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1116
1145
 					};
1117
1146
 					map1 {
1118
1147
 						trip = <&target>;
1119
1148
 						contribution = <512>;
1120
-						cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1149
+						cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1150
+								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1151
+								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1152
+								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1121
1153
 					};
1122
1154
 				};
1123
1155
 			};
1124
1156
 		};
1157
+
1158
+		usb3_otg_bc: usb3_otg_bc@ff200000 {
1159
+			compatible = "syscon", "simple-mfd";
1160
+			reg = <0x0 0xff200000 0x0 0x1000>;
1161
+
1162
+			usb_phy: usb-phy {
1163
+				compatible = "hisilicon,hi3660-usb-phy";
1164
+				#phy-cells = <0>;
1165
+				hisilicon,pericrg-syscon = <&crg_ctrl>;
1166
+				hisilicon,pctrl-syscon = <&pctrl>;
1167
+				hisilicon,eye-diagram-param = <0x22466e4>;
1168
+			};
1169
+		};
1170
+
1171
+		dwc3: dwc3@ff100000 {
1172
+			compatible = "snps,dwc3";
1173
+			reg = <0x0 0xff100000 0x0 0x100000>;
1174
+
1175
+			clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
1176
+				 <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1177
+			clock-names = "ref", "bus_early";
1178
+
1179
+			assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1180
+			assigned-clock-rates = <229000000>;
1181
+
1182
+			resets = <&crg_rst 0x90 8>,
1183
+				 <&crg_rst 0x90 7>,
1184
+				 <&crg_rst 0x90 6>,
1185
+				 <&crg_rst 0x90 5>;
1186
+
1187
+			interrupts = <0 159 4>, <0 161 4>;
1188
+			phys = <&usb_phy>;
1189
+			phy-names = "usb3-phy";
1190
+		};
1125
1191
 	};
1126
1192
 };
1193
+
1194
+#include "hi3660-coresight.dtsi"