forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/arch/arm/mach-rpc/irq.c
....@@ -8,110 +8,64 @@
88 #include <asm/irq.h>
99 #include <asm/fiq.h>
1010 
11
-static void iomd_ack_irq_a(struct irq_data *d)
12
-{
13
-	unsigned int val, mask;
11
+// These are offsets from the stat register for each IRQ bank
12
+#define STAT	0x00
13
+#define REQ	0x04
14
+#define CLR	0x04
15
+#define MASK	0x08
1416 
15
-	mask = 1 << d->irq;
16
-	val = iomd_readb(IOMD_IRQMASKA);
17
-	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
18
-	iomd_writeb(mask, IOMD_IRQCLRA);
17
+static void __iomem *iomd_get_base(struct irq_data *d)
18
+{
19
+	void *cd = irq_data_get_irq_chip_data(d);
20
+
21
+	return (void __iomem *)(unsigned long)cd;
1922 }
2023 
21
-static void iomd_mask_irq_a(struct irq_data *d)
24
+static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask)
2225 {
23
-	unsigned int val, mask;
26
+	struct irq_data *d = irq_get_irq_data(irq);
2427 
25
-	mask = 1 << d->irq;
26
-	val = iomd_readb(IOMD_IRQMASKA);
27
-	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
28
+	d->mask = mask;
29
+	irq_set_chip_data(irq, (void *)(unsigned long)base);
2830 }
2931 
30
-static void iomd_unmask_irq_a(struct irq_data *d)
32
+static void iomd_irq_mask_ack(struct irq_data *d)
3133 {
32
-	unsigned int val, mask;
34
+	void __iomem *base = iomd_get_base(d);
35
+	unsigned int val, mask = d->mask;
3336 
34
-	mask = 1 << d->irq;
35
-	val = iomd_readb(IOMD_IRQMASKA);
36
-	iomd_writeb(val | mask, IOMD_IRQMASKA);
37
+	val = readb(base + MASK);
38
+	writeb(val & ~mask, base + MASK);
39
+	writeb(mask, base + CLR);
3740 }
3841 
39
-static struct irq_chip iomd_a_chip = {
40
-	.irq_ack	= iomd_ack_irq_a,
41
-	.irq_mask	= iomd_mask_irq_a,
42
-	.irq_unmask	= iomd_unmask_irq_a,
42
+static void iomd_irq_mask(struct irq_data *d)
43
+{
44
+	void __iomem *base = iomd_get_base(d);
45
+	unsigned int val, mask = d->mask;
46
+
47
+	val = readb(base + MASK);
48
+	writeb(val & ~mask, base + MASK);
49
+}
50
+
51
+static void iomd_irq_unmask(struct irq_data *d)
52
+{
53
+	void __iomem *base = iomd_get_base(d);
54
+	unsigned int val, mask = d->mask;
55
+
56
+	val = readb(base + MASK);
57
+	writeb(val | mask, base + MASK);
58
+}
59
+
60
+static struct irq_chip iomd_chip_clr = {
61
+	.irq_mask_ack	= iomd_irq_mask_ack,
62
+	.irq_mask	= iomd_irq_mask,
63
+	.irq_unmask	= iomd_irq_unmask,
4364 };
4465 
45
-static void iomd_mask_irq_b(struct irq_data *d)
46
-{
47
-	unsigned int val, mask;
48
-
49
-	mask = 1 << (d->irq & 7);
50
-	val = iomd_readb(IOMD_IRQMASKB);
51
-	iomd_writeb(val & ~mask, IOMD_IRQMASKB);
52
-}
53
-
54
-static void iomd_unmask_irq_b(struct irq_data *d)
55
-{
56
-	unsigned int val, mask;
57
-
58
-	mask = 1 << (d->irq & 7);
59
-	val = iomd_readb(IOMD_IRQMASKB);
60
-	iomd_writeb(val | mask, IOMD_IRQMASKB);
61
-}
62
-
63
-static struct irq_chip iomd_b_chip = {
64
-	.irq_ack	= iomd_mask_irq_b,
65
-	.irq_mask	= iomd_mask_irq_b,
66
-	.irq_unmask	= iomd_unmask_irq_b,
67
-};
68
-
69
-static void iomd_mask_irq_dma(struct irq_data *d)
70
-{
71
-	unsigned int val, mask;
72
-
73
-	mask = 1 << (d->irq & 7);
74
-	val = iomd_readb(IOMD_DMAMASK);
75
-	iomd_writeb(val & ~mask, IOMD_DMAMASK);
76
-}
77
-
78
-static void iomd_unmask_irq_dma(struct irq_data *d)
79
-{
80
-	unsigned int val, mask;
81
-
82
-	mask = 1 << (d->irq & 7);
83
-	val = iomd_readb(IOMD_DMAMASK);
84
-	iomd_writeb(val | mask, IOMD_DMAMASK);
85
-}
86
-
87
-static struct irq_chip iomd_dma_chip = {
88
-	.irq_ack	= iomd_mask_irq_dma,
89
-	.irq_mask	= iomd_mask_irq_dma,
90
-	.irq_unmask	= iomd_unmask_irq_dma,
91
-};
92
-
93
-static void iomd_mask_irq_fiq(struct irq_data *d)
94
-{
95
-	unsigned int val, mask;
96
-
97
-	mask = 1 << (d->irq & 7);
98
-	val = iomd_readb(IOMD_FIQMASK);
99
-	iomd_writeb(val & ~mask, IOMD_FIQMASK);
100
-}
101
-
102
-static void iomd_unmask_irq_fiq(struct irq_data *d)
103
-{
104
-	unsigned int val, mask;
105
-
106
-	mask = 1 << (d->irq & 7);
107
-	val = iomd_readb(IOMD_FIQMASK);
108
-	iomd_writeb(val | mask, IOMD_FIQMASK);
109
-}
110
-
111
-static struct irq_chip iomd_fiq_chip = {
112
-	.irq_ack	= iomd_mask_irq_fiq,
113
-	.irq_mask	= iomd_mask_irq_fiq,
114
-	.irq_unmask	= iomd_unmask_irq_fiq,
66
+static struct irq_chip iomd_chip_noclr = {
67
+	.irq_mask	= iomd_irq_mask,
68
+	.irq_unmask	= iomd_irq_unmask,
11569 };
11670 
11771 extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
....@@ -141,30 +95,37 @@
14195 
14296 		switch (irq) {
14397 		case 0 ... 7:
144
-			irq_set_chip_and_handler(irq, &iomd_a_chip,
98
+			irq_set_chip_and_handler(irq, &iomd_chip_clr,
14599 						 handle_level_irq);
146100 			irq_modify_status(irq, clr, set);
101
+			iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA,
102
+					   BIT(irq));
147103 			break;
148104 
149105 		case 8 ... 15:
150
-			irq_set_chip_and_handler(irq, &iomd_b_chip,
106
+			irq_set_chip_and_handler(irq, &iomd_chip_noclr,
151107 						 handle_level_irq);
152108 			irq_modify_status(irq, clr, set);
109
+			iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB,
110
+					   BIT(irq - 8));
153111 			break;
154112 
155113 		case 16 ... 21:
156
-			irq_set_chip_and_handler(irq, &iomd_dma_chip,
114
+			irq_set_chip_and_handler(irq, &iomd_chip_noclr,
157115 						 handle_level_irq);
158116 			irq_modify_status(irq, clr, set);
117
+			iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT,
118
+					   BIT(irq - 16));
159119 			break;
160120 
161121 		case 64 ... 71:
162
-			irq_set_chip(irq, &iomd_fiq_chip);
122
+			irq_set_chip(irq, &iomd_chip_noclr);
163123 			irq_modify_status(irq, clr, set);
124
+			iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT,
125
+					   BIT(irq - 64));
164126 			break;
165127 		}
166128 	}
167129 
168130 	init_FIQ(FIQ_START);
169131 }
170
-