forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/arch/arm/mach-ixp4xx/common.c
....@@ -22,41 +22,29 @@
2222 #include <linux/serial_core.h>
2323 #include <linux/interrupt.h>
2424 #include <linux/bitops.h>
25
-#include <linux/time.h>
26
-#include <linux/clocksource.h>
27
-#include <linux/clockchips.h>
2825 #include <linux/io.h>
2926 #include <linux/export.h>
30
-#include <linux/gpio/driver.h>
3127 #include <linux/cpu.h>
3228 #include <linux/pci.h>
3329 #include <linux/sched_clock.h>
30
+#include <linux/irqchip/irq-ixp4xx.h>
31
+#include <linux/platform_data/timer-ixp4xx.h>
32
+#include <linux/dma-map-ops.h>
3433 #include <mach/udc.h>
3534 #include <mach/hardware.h>
3635 #include <mach/io.h>
3736 #include <linux/uaccess.h>
38
-#include <asm/pgtable.h>
3937 #include <asm/page.h>
38
+#include <asm/exception.h>
4039 #include <asm/irq.h>
4140 #include <asm/system_misc.h>
4241 #include <asm/mach/map.h>
4342 #include <asm/mach/irq.h>
4443 #include <asm/mach/time.h>
4544 
45
+#include "irqs.h"
46
+
4647 #define IXP4XX_TIMER_FREQ 66666000
47
-
48
-/*
49
- * The timer register doesn't allow to specify the two least significant bits of
50
- * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is
51
- * the best value with the two least significant bits unset.
52
- */
53
-#define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \
54
-				       (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
55
-			(IXP4XX_OST_RELOAD_MASK + 1)
56
-
57
-static void __init ixp4xx_clocksource_init(void);
58
-static void __init ixp4xx_clockevent_init(void);
59
-static struct clock_event_device clockevent_ixp4xx;
6048 
6149 /*************************************************************************
6250  * IXP4xx chipset I/O mapping
....@@ -77,11 +65,6 @@
7765 		.pfn		= __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
7866 		.length		= IXP4XX_PCI_CFG_REGION_SIZE,
7967 		.type		= MT_DEVICE
80
-	}, {	/* Queue Manager */
81
-		.virtual	= (unsigned long)IXP4XX_QMGR_BASE_VIRT,
82
-		.pfn		= __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
83
-		.length		= IXP4XX_QMGR_REGION_SIZE,
84
-		.type		= MT_DEVICE
8568 	},
8669 };
8770 
....@@ -90,258 +73,23 @@
9073   	iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
9174 }
9275 
93
-/*
94
- * GPIO-functions
95
- */
96
-/*
97
- * The following converted to the real HW bits the gpio_line_config
98
- */
99
-/* GPIO pin types */
100
-#define IXP4XX_GPIO_OUT 		0x1
101
-#define IXP4XX_GPIO_IN  		0x2
102
-
103
-/* GPIO signal types */
104
-#define IXP4XX_GPIO_LOW			0
105
-#define IXP4XX_GPIO_HIGH		1
106
-
107
-/* GPIO Clocks */
108
-#define IXP4XX_GPIO_CLK_0		14
109
-#define IXP4XX_GPIO_CLK_1		15
110
-
111
-static void gpio_line_config(u8 line, u32 direction)
112
-{
113
-	if (direction == IXP4XX_GPIO_IN)
114
-		*IXP4XX_GPIO_GPOER |= (1 << line);
115
-	else
116
-		*IXP4XX_GPIO_GPOER &= ~(1 << line);
117
-}
118
-
119
-static void gpio_line_get(u8 line, int *value)
120
-{
121
-	*value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
122
-}
123
-
124
-static void gpio_line_set(u8 line, int value)
125
-{
126
-	if (value == IXP4XX_GPIO_HIGH)
127
-	    *IXP4XX_GPIO_GPOUTR |= (1 << line);
128
-	else if (value == IXP4XX_GPIO_LOW)
129
-	    *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
130
-}
131
-
132
-/*************************************************************************
133
- * IXP4xx chipset IRQ handling
134
- *
135
- * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
136
- *       (be it PCI or something else) configures that GPIO line
137
- *       as an IRQ.
138
- **************************************************************************/
139
-enum ixp4xx_irq_type {
140
-	IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
141
-};
142
-
143
-/* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
144
-static unsigned long long ixp4xx_irq_edge = 0;
145
-
146
-/*
147
- * IRQ -> GPIO mapping table
148
- */
149
-static signed char irq2gpio[32] = {
150
-	-1, -1, -1, -1, -1, -1,  0,  1,
151
-	-1, -1, -1, -1, -1, -1, -1, -1,
152
-	-1, -1, -1,  2,  3,  4,  5,  6,
153
-	 7,  8,  9, 10, 11, 12, -1, -1,
154
-};
155
-
156
-static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
157
-{
158
-	int irq;
159
-
160
-	for (irq = 0; irq < 32; irq++) {
161
-		if (irq2gpio[irq] == gpio)
162
-			return irq;
163
-	}
164
-	return -EINVAL;
165
-}
166
-
167
-static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
168
-{
169
-	int line = irq2gpio[d->irq];
170
-	u32 int_style;
171
-	enum ixp4xx_irq_type irq_type;
172
-	volatile u32 *int_reg;
173
-
174
-	/*
175
-	 * Only for GPIO IRQs
176
-	 */
177
-	if (line < 0)
178
-		return -EINVAL;
179
-
180
-	switch (type){
181
-	case IRQ_TYPE_EDGE_BOTH:
182
-		int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
183
-		irq_type = IXP4XX_IRQ_EDGE;
184
-		break;
185
-	case IRQ_TYPE_EDGE_RISING:
186
-		int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
187
-		irq_type = IXP4XX_IRQ_EDGE;
188
-		break;
189
-	case IRQ_TYPE_EDGE_FALLING:
190
-		int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
191
-		irq_type = IXP4XX_IRQ_EDGE;
192
-		break;
193
-	case IRQ_TYPE_LEVEL_HIGH:
194
-		int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
195
-		irq_type = IXP4XX_IRQ_LEVEL;
196
-		break;
197
-	case IRQ_TYPE_LEVEL_LOW:
198
-		int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
199
-		irq_type = IXP4XX_IRQ_LEVEL;
200
-		break;
201
-	default:
202
-		return -EINVAL;
203
-	}
204
-
205
-	if (irq_type == IXP4XX_IRQ_EDGE)
206
-		ixp4xx_irq_edge |= (1 << d->irq);
207
-	else
208
-		ixp4xx_irq_edge &= ~(1 << d->irq);
209
-
210
-	if (line >= 8) {	/* pins 8-15 */
211
-		line -= 8;
212
-		int_reg = IXP4XX_GPIO_GPIT2R;
213
-	} else {		/* pins 0-7 */
214
-		int_reg = IXP4XX_GPIO_GPIT1R;
215
-	}
216
-
217
-	/* Clear the style for the appropriate pin */
218
-	*int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
219
-	    		(line * IXP4XX_GPIO_STYLE_SIZE));
220
-
221
-	*IXP4XX_GPIO_GPISR = (1 << line);
222
-
223
-	/* Set the new style */
224
-	*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
225
-
226
-	/* Configure the line as an input */
227
-	gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
228
-
229
-	return 0;
230
-}
231
-
232
-static void ixp4xx_irq_mask(struct irq_data *d)
233
-{
234
-	if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
235
-		*IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
236
-	else
237
-		*IXP4XX_ICMR &= ~(1 << d->irq);
238
-}
239
-
240
-static void ixp4xx_irq_ack(struct irq_data *d)
241
-{
242
-	int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
243
-
244
-	if (line >= 0)
245
-		*IXP4XX_GPIO_GPISR = (1 << line);
246
-}
247
-
248
-/*
249
- * Level triggered interrupts on GPIO lines can only be cleared when the
250
- * interrupt condition disappears.
251
- */
252
-static void ixp4xx_irq_unmask(struct irq_data *d)
253
-{
254
-	if (!(ixp4xx_irq_edge & (1 << d->irq)))
255
-		ixp4xx_irq_ack(d);
256
-
257
-	if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
258
-		*IXP4XX_ICMR2 |= (1 << (d->irq - 32));
259
-	else
260
-		*IXP4XX_ICMR |= (1 << d->irq);
261
-}
262
-
263
-static struct irq_chip ixp4xx_irq_chip = {
264
-	.name		= "IXP4xx",
265
-	.irq_ack	= ixp4xx_irq_ack,
266
-	.irq_mask	= ixp4xx_irq_mask,
267
-	.irq_unmask	= ixp4xx_irq_unmask,
268
-	.irq_set_type	= ixp4xx_set_irq_type,
269
-};
270
-
27176 void __init ixp4xx_init_irq(void)
27277 {
273
-	int i = 0;
274
-
27578 	/*
27679 	 * ixp4xx does not implement the XScale PWRMODE register
27780 	 * so it must not call cpu_do_idle().
27881 	 */
27982 	cpu_idle_poll_ctrl(true);
28083 
281
-	/* Route all sources to IRQ instead of FIQ */
282
-	*IXP4XX_ICLR = 0x0;
283
-
284
-	/* Disable all interrupt */
285
-	*IXP4XX_ICMR = 0x0; 
286
-
287
-	if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
288
-		/* Route upper 32 sources to IRQ instead of FIQ */
289
-		*IXP4XX_ICLR2 = 0x00;
290
-
291
-		/* Disable upper 32 interrupts */
292
-		*IXP4XX_ICMR2 = 0x00;
293
-	}
294
-
295
-        /* Default to all level triggered */
296
-	for(i = 0; i < NR_IRQS; i++) {
297
-		irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
298
-					 handle_level_irq);
299
-		irq_clear_status_flags(i, IRQ_NOREQUEST);
300
-	}
84
+	ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
85
+			(cpu_is_ixp46x() || cpu_is_ixp43x()));
30186 }
302
-
303
-
304
-/*************************************************************************
305
- * IXP4xx timer tick
306
- * We use OS timer1 on the CPU for the timer tick and the timestamp 
307
- * counter as a source of real clock ticks to account for missed jiffies.
308
- *************************************************************************/
309
-
310
-static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
311
-{
312
-	struct clock_event_device *evt = dev_id;
313
-
314
-	/* Clear Pending Interrupt by writing '1' to it */
315
-	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
316
-
317
-	evt->event_handler(evt);
318
-
319
-	return IRQ_HANDLED;
320
-}
321
-
322
-static struct irqaction ixp4xx_timer_irq = {
323
-	.name		= "timer1",
324
-	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
325
-	.handler	= ixp4xx_timer_interrupt,
326
-	.dev_id		= &clockevent_ixp4xx,
327
-};
32887 
32988 void __init ixp4xx_timer_init(void)
33089 {
331
-	/* Reset/disable counter */
332
-	*IXP4XX_OSRT1 = 0;
333
-
334
-	/* Clear Pending Interrupt by writing '1' to it */
335
-	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
336
-
337
-	/* Reset time-stamp counter */
338
-	*IXP4XX_OSTS = 0;
339
-
340
-	/* Connect the interrupt handler and enable the interrupt */
341
-	setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
342
-
343
-	ixp4xx_clocksource_init();
344
-	ixp4xx_clockevent_init();
90
+	return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,
91
+				  IRQ_IXP4XX_TIMER1,
92
+				  IXP4XX_TIMER_FREQ);
34593 }
34694 
34795 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
....@@ -364,6 +112,24 @@
364112 	},
365113 };
366114 
115
+static struct resource ixp4xx_gpio_resource[] = {
116
+	{
117
+		.start = IXP4XX_GPIO_BASE_PHYS,
118
+		.end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
119
+		.flags = IORESOURCE_MEM,
120
+	},
121
+};
122
+
123
+static struct platform_device ixp4xx_gpio_device = {
124
+	.name           = "ixp4xx-gpio",
125
+	.id             = -1,
126
+	.dev = {
127
+		.coherent_dma_mask      = DMA_BIT_MASK(32),
128
+	},
129
+	.resource = ixp4xx_gpio_resource,
130
+	.num_resources  = ARRAY_SIZE(ixp4xx_gpio_resource),
131
+};
132
+
367133 /*
368134  * USB device controller. The IXP4xx uses the same controller as PXA25X,
369135  * so we just use the same device.
....@@ -378,7 +144,61 @@
378144 	},
379145 };
380146 
147
+static struct resource ixp4xx_npe_resources[] = {
148
+	{
149
+		.start = IXP4XX_NPEA_BASE_PHYS,
150
+		.end = IXP4XX_NPEA_BASE_PHYS + 0xfff,
151
+		.flags = IORESOURCE_MEM,
152
+	},
153
+	{
154
+		.start = IXP4XX_NPEB_BASE_PHYS,
155
+		.end = IXP4XX_NPEB_BASE_PHYS + 0xfff,
156
+		.flags = IORESOURCE_MEM,
157
+	},
158
+	{
159
+		.start = IXP4XX_NPEC_BASE_PHYS,
160
+		.end = IXP4XX_NPEC_BASE_PHYS + 0xfff,
161
+		.flags = IORESOURCE_MEM,
162
+	},
163
+
164
+};
165
+
166
+static struct platform_device ixp4xx_npe_device = {
167
+	.name           = "ixp4xx-npe",
168
+	.id             = -1,
169
+	.num_resources  = ARRAY_SIZE(ixp4xx_npe_resources),
170
+	.resource       = ixp4xx_npe_resources,
171
+};
172
+
173
+static struct resource ixp4xx_qmgr_resources[] = {
174
+	{
175
+		.start = IXP4XX_QMGR_BASE_PHYS,
176
+		.end = IXP4XX_QMGR_BASE_PHYS + 0x3fff,
177
+		.flags = IORESOURCE_MEM,
178
+	},
179
+	{
180
+		.start = IRQ_IXP4XX_QM1,
181
+		.end = IRQ_IXP4XX_QM1,
182
+		.flags = IORESOURCE_IRQ,
183
+	},
184
+	{
185
+		.start = IRQ_IXP4XX_QM2,
186
+		.end = IRQ_IXP4XX_QM2,
187
+		.flags = IORESOURCE_IRQ,
188
+	},
189
+};
190
+
191
+static struct platform_device ixp4xx_qmgr_device = {
192
+	.name           = "ixp4xx-qmgr",
193
+	.id             = -1,
194
+	.num_resources  = ARRAY_SIZE(ixp4xx_qmgr_resources),
195
+	.resource       = ixp4xx_qmgr_resources,
196
+};
197
+
381198 static struct platform_device *ixp4xx_devices[] __initdata = {
199
+	&ixp4xx_npe_device,
200
+	&ixp4xx_qmgr_device,
201
+	&ixp4xx_gpio_device,
382202 	&ixp4xx_udc_device,
383203 };
384204 
....@@ -413,55 +233,11 @@
413233 unsigned long ixp4xx_exp_bus_size;
414234 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
415235 
416
-static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
417
-{
418
-	gpio_line_config(gpio, IXP4XX_GPIO_IN);
419
-
420
-	return 0;
421
-}
422
-
423
-static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
424
-					int level)
425
-{
426
-	gpio_line_set(gpio, level);
427
-	gpio_line_config(gpio, IXP4XX_GPIO_OUT);
428
-
429
-	return 0;
430
-}
431
-
432
-static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
433
-{
434
-	int value;
435
-
436
-	gpio_line_get(gpio, &value);
437
-
438
-	return value;
439
-}
440
-
441
-static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
442
-				  int value)
443
-{
444
-	gpio_line_set(gpio, value);
445
-}
446
-
447
-static struct gpio_chip ixp4xx_gpio_chip = {
448
-	.label			= "IXP4XX_GPIO_CHIP",
449
-	.direction_input	= ixp4xx_gpio_direction_input,
450
-	.direction_output	= ixp4xx_gpio_direction_output,
451
-	.get			= ixp4xx_gpio_get_value,
452
-	.set			= ixp4xx_gpio_set_value,
453
-	.to_irq			= ixp4xx_gpio_to_irq,
454
-	.base			= 0,
455
-	.ngpio			= 16,
456
-};
457
-
458236 void __init ixp4xx_sys_init(void)
459237 {
460238 	ixp4xx_exp_bus_size = SZ_16M;
461239 
462240 	platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
463
-
464
-	gpiochip_add_data(&ixp4xx_gpio_chip, NULL);
465241 
466242 	if (cpu_is_ixp46x()) {
467243 		int region;
....@@ -481,103 +257,8 @@
481257 			ixp4xx_exp_bus_size >> 20);
482258 }
483259 
484
-/*
485
- * sched_clock()
486
- */
487
-static u64 notrace ixp4xx_read_sched_clock(void)
488
-{
489
-	return *IXP4XX_OSTS;
490
-}
491
-
492
-/*
493
- * clocksource
494
- */
495
-
496
-static u64 ixp4xx_clocksource_read(struct clocksource *c)
497
-{
498
-	return *IXP4XX_OSTS;
499
-}
500
-
501260 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
502261 EXPORT_SYMBOL(ixp4xx_timer_freq);
503
-static void __init ixp4xx_clocksource_init(void)
504
-{
505
-	sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
506
-
507
-	clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
508
-			ixp4xx_clocksource_read);
509
-}
510
-
511
-/*
512
- * clockevents
513
- */
514
-static int ixp4xx_set_next_event(unsigned long evt,
515
-				 struct clock_event_device *unused)
516
-{
517
-	unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
518
-
519
-	*IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
520
-
521
-	return 0;
522
-}
523
-
524
-static int ixp4xx_shutdown(struct clock_event_device *evt)
525
-{
526
-	unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
527
-	unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
528
-
529
-	opts &= ~IXP4XX_OST_ENABLE;
530
-	*IXP4XX_OSRT1 = osrt | opts;
531
-	return 0;
532
-}
533
-
534
-static int ixp4xx_set_oneshot(struct clock_event_device *evt)
535
-{
536
-	unsigned long opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
537
-	unsigned long osrt = 0;
538
-
539
-	/* period set by 'set next_event' */
540
-	*IXP4XX_OSRT1 = osrt | opts;
541
-	return 0;
542
-}
543
-
544
-static int ixp4xx_set_periodic(struct clock_event_device *evt)
545
-{
546
-	unsigned long opts = IXP4XX_OST_ENABLE;
547
-	unsigned long osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
548
-
549
-	*IXP4XX_OSRT1 = osrt | opts;
550
-	return 0;
551
-}
552
-
553
-static int ixp4xx_resume(struct clock_event_device *evt)
554
-{
555
-	unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
556
-	unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
557
-
558
-	opts |= IXP4XX_OST_ENABLE;
559
-	*IXP4XX_OSRT1 = osrt | opts;
560
-	return 0;
561
-}
562
-
563
-static struct clock_event_device clockevent_ixp4xx = {
564
-	.name			= "ixp4xx timer1",
565
-	.features		= CLOCK_EVT_FEAT_PERIODIC |
566
-				  CLOCK_EVT_FEAT_ONESHOT,
567
-	.rating			= 200,
568
-	.set_state_shutdown	= ixp4xx_shutdown,
569
-	.set_state_periodic	= ixp4xx_set_periodic,
570
-	.set_state_oneshot	= ixp4xx_set_oneshot,
571
-	.tick_resume		= ixp4xx_resume,
572
-	.set_next_event		= ixp4xx_set_next_event,
573
-};
574
-
575
-static void __init ixp4xx_clockevent_init(void)
576
-{
577
-	clockevent_ixp4xx.cpumask = cpumask_of(0);
578
-	clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
579
-					0xf, 0xfffffffe);
580
-}
581262 
582263 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
583264 {