.. | .. |
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64 | 64 | |
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65 | 65 | csi_dphy_input0: endpoint@0 { |
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66 | 66 | reg = <0>; |
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67 | | - remote-endpoint = <&sc3338_30_out>; |
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| 67 | + remote-endpoint = <&sc301iot_out>; |
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68 | 68 | data-lanes = <1 2>; |
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69 | 69 | }; |
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70 | 70 | }; |
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.. | .. |
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96 | 96 | |
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97 | 97 | csi_dphy_input1: endpoint@0 { |
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98 | 98 | reg = <0>; |
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99 | | - remote-endpoint = <&sc3338_32_out>; |
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| 99 | + remote-endpoint = <&sc230ai_out>; |
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100 | 100 | data-lanes = <1 2>; |
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101 | 101 | }; |
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102 | 102 | }; |
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.. | .. |
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127 | 127 | &i2c4 { |
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128 | 128 | rockchip,amp-shared; |
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129 | 129 | |
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130 | | - sc3338_30: sc3338_30@30 { |
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131 | | - compatible = "smartsens,sc3338"; |
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| 130 | + sc230ai: sc230ai@30 { |
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| 131 | + compatible = "smartsens,sc230ai"; |
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132 | 132 | status = "okay"; |
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133 | 133 | reg = <0x30>; |
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134 | | - clocks = <&cru MCLK_REF_MIPI0>; |
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| 134 | + clocks = <&cru MCLK_REF_MIPI1>; |
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135 | 135 | clock-names = "xvclk"; |
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136 | | - pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; |
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| 136 | + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; |
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137 | 137 | pinctrl-names = "default"; |
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138 | | - pinctrl-0 = <&mipi_refclk_out0>; |
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139 | | - rockchip,camera-module-index = <0>; |
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| 138 | + pinctrl-0 = <&mipi_refclk_out1>; |
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| 139 | + rockchip,camera-module-index = <1>; |
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140 | 140 | rockchip,camera-module-facing = "back"; |
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141 | | - rockchip,camera-module-name = "FKO1"; |
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142 | | - rockchip,camera-module-lens-name = "30IRC-F16"; |
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| 141 | + rockchip,camera-module-name = "CMK-OT2350-PC1"; |
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| 142 | + rockchip,camera-module-lens-name = "65IRC-F16"; |
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143 | 143 | port { |
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144 | | - sc3338_30_out: endpoint { |
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145 | | - remote-endpoint = <&csi_dphy_input0>; |
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| 144 | + sc230ai_out: endpoint { |
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| 145 | + remote-endpoint = <&csi_dphy_input1>; |
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146 | 146 | data-lanes = <1 2>; |
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147 | 147 | }; |
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148 | 148 | }; |
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149 | 149 | }; |
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150 | 150 | |
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151 | | - sc3338_32: sc3338_32@32 { |
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152 | | - compatible = "smartsens,sc3338"; |
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| 151 | + sc301iot: sc301iot@32 { |
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| 152 | + compatible = "smartsens,sc301iot"; |
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153 | 153 | status = "okay"; |
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154 | 154 | reg = <0x32>; |
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155 | | - clocks = <&cru MCLK_REF_MIPI1>; |
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| 155 | + clocks = <&cru MCLK_REF_MIPI0>; |
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156 | 156 | clock-names = "xvclk"; |
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157 | | - pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; |
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| 157 | + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; |
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| 158 | + pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; |
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158 | 159 | pinctrl-names = "default"; |
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159 | | - pinctrl-0 = <&mipi_refclk_out1>; |
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160 | | - rockchip,camera-module-index = <1>; |
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| 160 | + pinctrl-0 = <&mipi_refclk_out0>; |
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| 161 | + rockchip,camera-module-index = <0>; |
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161 | 162 | rockchip,camera-module-facing = "back"; |
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162 | | - rockchip,camera-module-name = "FKO1"; |
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163 | | - rockchip,camera-module-lens-name = "30IRC-F16"; |
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| 163 | + rockchip,camera-module-name = "CMK-OT2349-PC1"; |
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| 164 | + rockchip,camera-module-lens-name = "65IRC-F20"; |
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164 | 165 | port { |
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165 | | - sc3338_32_out: endpoint { |
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166 | | - remote-endpoint = <&csi_dphy_input1>; |
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| 166 | + sc301iot_out: endpoint { |
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| 167 | + remote-endpoint = <&csi_dphy_input0>; |
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167 | 168 | data-lanes = <1 2>; |
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168 | 169 | }; |
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169 | 170 | }; |
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.. | .. |
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327 | 328 | /* reg's offset MUST match with RTOS */ |
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328 | 329 | /* |
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329 | 330 | * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) |
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330 | | - * e.g. 2304x1296: 0xf30000 |
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| 331 | + * e.g. 2048x1536: 0xf00000 |
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331 | 332 | * 0x008b0000 = (meta's reg offset) + (meta's reg size) |
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332 | 333 | * = 0x00800000 + 0xb0000 |
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333 | 334 | */ |
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334 | | - reg = <0x008b0000 0xf30000>; |
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| 335 | + reg = <0x008b0000 0xf00000>; |
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335 | 336 | }; |
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336 | 337 | |
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337 | 338 | &ramdisk_r { |
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338 | | - reg = <0x17e0000 (10 * 0x00100000)>; |
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| 339 | + reg = <0x17b0000 (10 * 0x00100000)>; |
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339 | 340 | }; |
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340 | 341 | |
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341 | 342 | &ramdisk_c { |
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342 | | - reg = <0x21e0000 (5 * 0x00100000)>; |
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| 343 | + reg = <0x21b0000 (5 * 0x00100000)>; |
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343 | 344 | }; |
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344 | 345 | |
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345 | 346 | &rkisp1_thunderboot { |
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346 | 347 | /* |
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347 | 348 | * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) |
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348 | | - * e.g. 2304x1296: 0xf30000 |
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349 | | - * 0x26e0000 = (ramdisk_c's reg offset) + (ramdisk_c's reg size) |
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350 | | - * = 0x21e0000 + (5 * 0x00100000) |
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| 349 | + * e.g. 1920x1080: 0xa8c0000 |
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| 350 | + * 0x26b0000 = (ramdisk_c's reg offset) + (ramdisk_c's reg size) |
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| 351 | + * = 0x21b0000 + (5 * 0x00100000) |
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351 | 352 | */ |
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352 | | - reg = <0x26e0000 0xf30000>; |
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| 353 | + reg = <0x26b0000 0xa8c000>; |
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353 | 354 | }; |
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354 | 355 | |
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355 | 356 | &pinctrl { |
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