kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm/boot/dts/hi3620.dtsi
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Hisilicon Ltd. Hi3620 SoC
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  *
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@@ -5,10 +6,6 @@
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  * Copyright (C) 2012-2013 Linaro Ltd.
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  *
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  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * publishhed by the Free Software Foundation.
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  */
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 #include <dt-bindings/clock/hi3620-clock.h>
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 		interrupt-parent = <&gic>;
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 		ranges = <0 0xfc000000 0x2000000>;
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-		L2: l2-cache {
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+		L2: cache-controller {
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 			compatible = "arm,pl310-cache";
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 			reg = <0x100000 0x100000>;
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 			interrupts = <0 15 4>;
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 		};
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 		sysctrl: system-controller@802000 {
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-			compatible = "hisilicon,sysctrl";
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+			compatible = "hisilicon,sysctrl", "syscon";
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 			#address-cells = <1>;
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 			#size-cells = <1>;
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 			ranges = <0 0x802000 0x1000>;
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@@ -114,8 +111,10 @@
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 			reg = <0x800000 0x1000>;
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 			/* timer00 & timer01 */
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 			interrupts = <0 0 4>, <0 1 4>;
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-			clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
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-			clock-names = "apb_pclk";
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+			clocks = <&clock HI3620_TIMER0_MUX>,
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+				 <&clock HI3620_TIMER1_MUX>,
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+				 <&clock HI3620_TIMER0_MUX>;
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+			clock-names = "timer0clk", "timer1clk", "apb_pclk";
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 			status = "disabled";
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 		};
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 			reg = <0x801000 0x1000>;
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 			/* timer10 & timer11 */
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 			interrupts = <0 2 4>, <0 3 4>;
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-			clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
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-			clock-names = "apb_pclk";
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+			clocks = <&clock HI3620_TIMER2_MUX>,
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+				 <&clock HI3620_TIMER3_MUX>,
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+				 <&clock HI3620_TIMER2_MUX>;
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+			clock-names = "timer0clk", "timer1clk", "apb_pclk";
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 			status = "disabled";
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 		};
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@@ -134,8 +135,10 @@
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 			reg = <0xa01000 0x1000>;
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 			/* timer20 & timer21 */
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 			interrupts = <0 4 4>, <0 5 4>;
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-			clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
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-			clock-names = "apb_pclk";
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+			clocks = <&clock HI3620_TIMER4_MUX>,
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+				 <&clock HI3620_TIMER5_MUX>,
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+				 <&clock HI3620_TIMER4_MUX>;
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+			clock-names = "timer0lck", "timer1clk", "apb_pclk";
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 			status = "disabled";
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 		};
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 			reg = <0xa02000 0x1000>;
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 			/* timer30 & timer31 */
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 			interrupts = <0 6 4>, <0 7 4>;
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-			clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
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-			clock-names = "apb_pclk";
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+			clocks = <&clock HI3620_TIMER6_MUX>,
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+				 <&clock HI3620_TIMER7_MUX>,
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+				 <&clock HI3620_TIMER6_MUX>;
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+			clock-names = "timer0clk", "timer1clk", "apb_pclk";
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 			status = "disabled";
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 		};
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 			reg = <0xa03000 0x1000>;
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 			/* timer40 & timer41 */
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 			interrupts = <0 96 4>, <0 97 4>;
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-			clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
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-			clock-names = "apb_pclk";
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+			clocks = <&clock HI3620_TIMER8_MUX>,
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+				 <&clock HI3620_TIMER9_MUX>,
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+				 <&clock HI3620_TIMER8_MUX>;
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+			clock-names = "timer0clk", "timer1clk", "apb_pclk";
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 			status = "disabled";
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 		};
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