kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arc/kernel/mcip.c
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@@ -1,11 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
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  *
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  * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/smp.h>
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@@ -205,8 +202,8 @@
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 	__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
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 }
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-static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
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-			   unsigned int distr)
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+static void idu_set_mode(unsigned int cmn_irq, bool set_lvl, unsigned int lvl,
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+			 bool set_distr, unsigned int distr)
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 {
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 	union {
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 		unsigned int word;
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@@ -215,8 +212,11 @@
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 		};
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 	} data;
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-	data.distr = distr;
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-	data.lvl = lvl;
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+	data.word = __mcip_cmd_read(CMD_IDU_READ_MODE, cmn_irq);
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+	if (set_distr)
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+		data.distr = distr;
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+	if (set_lvl)
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+		data.lvl = lvl;
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 	__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
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 }
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@@ -243,6 +243,25 @@
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 	raw_spin_unlock_irqrestore(&mcip_lock, flags);
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 }
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+static void idu_irq_ack(struct irq_data *data)
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+{
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+	unsigned long flags;
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+
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+	raw_spin_lock_irqsave(&mcip_lock, flags);
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+	__mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
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+	raw_spin_unlock_irqrestore(&mcip_lock, flags);
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+}
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+
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+static void idu_irq_mask_ack(struct irq_data *data)
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+{
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+	unsigned long flags;
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+
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+	raw_spin_lock_irqsave(&mcip_lock, flags);
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+	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
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+	__mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
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+	raw_spin_unlock_irqrestore(&mcip_lock, flags);
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+}
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+
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 static int
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 idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
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 		     bool force)
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@@ -266,11 +285,34 @@
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 	else
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 		distribution_mode = IDU_M_DISTRI_RR;
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-	idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode);
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+	idu_set_mode(data->hwirq, false, 0, true, distribution_mode);
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 	raw_spin_unlock_irqrestore(&mcip_lock, flags);
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 	return IRQ_SET_MASK_OK;
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+}
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+
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+static int idu_irq_set_type(struct irq_data *data, u32 type)
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+{
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+	unsigned long flags;
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+
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+	/*
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+	 * ARCv2 IDU HW does not support inverse polarity, so these are the
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+	 * only interrupt types supported.
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+	 */
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+	if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
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+		return -EINVAL;
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+
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+	raw_spin_lock_irqsave(&mcip_lock, flags);
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+
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+	idu_set_mode(data->hwirq, true,
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+		     type & IRQ_TYPE_EDGE_RISING ? IDU_M_TRIG_EDGE :
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+						   IDU_M_TRIG_LEVEL,
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+		     false, 0);
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+
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+	raw_spin_unlock_irqrestore(&mcip_lock, flags);
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+
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+	return 0;
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 }
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 static void idu_irq_enable(struct irq_data *data)
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@@ -292,7 +334,10 @@
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 	.name			= "MCIP IDU Intc",
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 	.irq_mask		= idu_irq_mask,
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 	.irq_unmask		= idu_irq_unmask,
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+	.irq_ack		= idu_irq_ack,
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+	.irq_mask_ack		= idu_irq_mask_ack,
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 	.irq_enable		= idu_irq_enable,
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+	.irq_set_type		= idu_irq_set_type,
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 #ifdef CONFIG_SMP
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 	.irq_set_affinity       = idu_irq_set_affinity,
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 #endif
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@@ -320,7 +365,7 @@
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 }
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 static const struct irq_domain_ops idu_irq_ops = {
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-	.xlate	= irq_domain_xlate_onecell,
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+	.xlate	= irq_domain_xlate_onetwocell,
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 	.map	= idu_irq_map,
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 };
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