kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arc/include/asm/bitops.h
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@@ -1,9 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef _ASM_BITOPS_H
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@@ -88,7 +85,7 @@
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 	return (old & (1 << nr)) != 0;					\
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 }
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-#elif !defined(CONFIG_ARC_PLAT_EZNPS)
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+#else /* !CONFIG_ARC_HAS_LLSC */
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 /*
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  * Non hardware assisted Atomic-R-M-W
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@@ -139,55 +136,7 @@
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 	return (old & (1UL << (nr & 0x1f))) != 0;			\
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 }
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-#else /* CONFIG_ARC_PLAT_EZNPS */
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-
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-#define BIT_OP(op, c_op, asm_op)					\
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-static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
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-{									\
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-	m += nr >> 5;							\
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-									\
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-	nr = (1UL << (nr & 0x1f));					\
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-	if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3)			\
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-		nr = ~nr;						\
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-									\
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-	__asm__ __volatile__(						\
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-	"	mov r2, %0\n"						\
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-	"	mov r3, %1\n"						\
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-	"	.word %2\n"						\
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-	:								\
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-	: "r"(nr), "r"(m), "i"(asm_op)					\
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-	: "r2", "r3", "memory");					\
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-}
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-
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-#define TEST_N_BIT_OP(op, c_op, asm_op)					\
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-static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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-{									\
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-	unsigned long old;						\
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-									\
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-	m += nr >> 5;							\
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-									\
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-	nr = old = (1UL << (nr & 0x1f));				\
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-	if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3)			\
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-		old = ~old;						\
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-									\
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-	/* Explicit full memory barrier needed before/after */		\
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-	smp_mb();							\
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-									\
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-	__asm__ __volatile__(						\
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-	"	mov r2, %0\n"						\
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-	"	mov r3, %1\n"						\
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-	"       .word %2\n"						\
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-	"	mov %0, r2"						\
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-	: "+r"(old)							\
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-	: "r"(m), "i"(asm_op)						\
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-	: "r2", "r3", "memory");					\
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-									\
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-	smp_mb();							\
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-									\
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-	return (old & nr) != 0;					\
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-}
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-
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-#endif /* CONFIG_ARC_PLAT_EZNPS */
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+#endif
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 /***************************************
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  * Non atomic variants
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@@ -229,15 +178,9 @@
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 	/* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
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 	__TEST_N_BIT_OP(op, c_op, asm_op)
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180
 
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-#ifndef CONFIG_ARC_PLAT_EZNPS
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 BIT_OPS(set, |, bset)
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 BIT_OPS(clear, & ~, bclr)
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 BIT_OPS(change, ^, bxor)
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-#else
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-BIT_OPS(set, |, CTOP_INST_AOR_DI_R2_R2_R3)
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-BIT_OPS(clear, & ~, CTOP_INST_AAND_DI_R2_R2_R3)
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-BIT_OPS(change, ^, CTOP_INST_AXOR_DI_R2_R2_R3)
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-#endif
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 /*
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  * This routine doesn't need to be atomic.
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@@ -278,7 +221,7 @@
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 	return res;
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 }
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-static inline int constant_fls(int x)
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+static inline int constant_fls(unsigned int x)
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 {
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 	int r = 32;
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@@ -300,10 +243,8 @@
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 		x <<= 2;
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 		r -= 2;
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 	}
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-	if (!(x & 0x80000000u)) {
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-		x <<= 1;
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+	if (!(x & 0x80000000u))
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 		r -= 1;
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-	}
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 	return r;
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 }
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@@ -312,7 +253,7 @@
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  * @result: [1-32]
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  * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
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  */
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-static inline __attribute__ ((const)) int fls(unsigned long x)
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+static inline __attribute__ ((const)) int fls(unsigned int x)
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 {
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 	if (__builtin_constant_p(x))
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 	       return constant_fls(x);