| .. | .. |
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| 446 | 446 | void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, |
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| 447 | 447 | enum dma_data_direction dir) |
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| 448 | 448 | { |
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| 449 | + /* |
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| 450 | + * fdc: The data cache line is written back to memory, if and only if |
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| 451 | + * it is dirty, and then invalidated from the data cache. |
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| 452 | + */ |
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| 449 | 453 | flush_kernel_dcache_range((unsigned long)phys_to_virt(paddr), size); |
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| 450 | 454 | } |
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| 451 | 455 | |
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| 452 | 456 | void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, |
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| 453 | 457 | enum dma_data_direction dir) |
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| 454 | 458 | { |
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| 455 | | - flush_kernel_dcache_range((unsigned long)phys_to_virt(paddr), size); |
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| 459 | + unsigned long addr = (unsigned long) phys_to_virt(paddr); |
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| 460 | + |
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| 461 | + switch (dir) { |
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| 462 | + case DMA_TO_DEVICE: |
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| 463 | + case DMA_BIDIRECTIONAL: |
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| 464 | + flush_kernel_dcache_range(addr, size); |
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| 465 | + return; |
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| 466 | + case DMA_FROM_DEVICE: |
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| 467 | + purge_kernel_dcache_range_asm(addr, addr + size); |
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| 468 | + return; |
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| 469 | + default: |
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| 470 | + BUG(); |
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| 471 | + } |
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| 456 | 472 | } |
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