~hc/RK356X_SDK_RELEASE.git

..	..	@@ -46,7 +46,7 @@
46	46	#include <dt-bindings/thermal/thermal.h>
47	47
48	48	/ {
49		- cpu0_opp_table: opp_table0 {
	49	+ cpu0_opp_table: opp-table-cpu {
50	50	compatible = "operating-points-v2";
51	51	opp-shared;
52	52
..	..	@@ -131,14 +131,14 @@
131	131	#cooling-cells = <2>;
132	132	};
133	133
134		- cpu@1 {
	134	+ cpu1: cpu@1 {
135	135	clocks = <&ccu CLK_CPUX>;
136	136	clock-names = "cpu";
137	137	operating-points-v2 = <&cpu0_opp_table>;
138	138	#cooling-cells = <2>;
139	139	};
140	140
141		- cpu@2 {
	141	+ cpu2: cpu@2 {
142	142	compatible = "arm,cortex-a7";
143	143	device_type = "cpu";
144	144	reg = <2>;
..	..	@@ -148,7 +148,7 @@
148	148	#cooling-cells = <2>;
149	149	};
150	150
151		- cpu@3 {
	151	+ cpu3: cpu@3 {
152	152	compatible = "arm,cortex-a7";
153	153	device_type = "cpu";
154	154	reg = <3>;
..	..	@@ -159,18 +159,12 @@
159	159	};
160	160	};
161	161
162		- de: display-engine {
163		- compatible = "allwinner,sun8i-a33-display-engine";
164		- allwinner,pipelines = <&fe0>;
165		- status = "disabled";
166		- };
167		-
168	162	iio-hwmon {
169	163	compatible = "iio-hwmon";
170	164	io-channels = <&ths>;
171	165	};
172	166
173		- mali_opp_table: gpu-opp-table {
	167	+ mali_opp_table: opp-table-gpu {
174	168	compatible = "operating-points-v2";
175	169
176	170	opp-144000000 {
..	..	@@ -186,21 +180,17 @@
186	180	};
187	181	};
188	182
189		- memory {
190		- reg = <0x40000000 0x80000000>;
191		- };
192		-
193	183	sound: sound {
194	184	compatible = "simple-audio-card";
195	185	simple-audio-card,name = "sun8i-a33-audio";
196	186	simple-audio-card,format = "i2s";
197	187	simple-audio-card,frame-master = <&link_codec>;
198	188	simple-audio-card,bitclock-master = <&link_codec>;
199		- simple-audio-card,mclk-fs = <512>;
	189	+ simple-audio-card,mclk-fs = <128>;
200	190	simple-audio-card,aux-devs = <&codec_analog>;
201	191	simple-audio-card,routing =
202		- "Left DAC", "AIF1 Slot 0 Left",
203		- "Right DAC", "AIF1 Slot 0 Right";
	192	+ "Left DAC", "DACL",
	193	+ "Right DAC", "DACR";
204	194	status = "disabled";
205	195
206	196	simple-audio-card,cpu {
..	..	@@ -212,50 +202,20 @@
212	202	};
213	203	};
214	204
215		- soc@1c00000 {
216		- tcon0: lcd-controller@1c0c000 {
217		- compatible = "allwinner,sun8i-a33-tcon";
218		- reg = <0x01c0c000 0x1000>;
219		- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
220		- clocks = <&ccu CLK_BUS_LCD>,
221		- <&ccu CLK_LCD_CH0>;
222		- clock-names = "ahb",
223		- "tcon-ch0";
224		- clock-output-names = "tcon-pixel-clock";
225		- resets = <&ccu RST_BUS_LCD>;
226		- reset-names = "lcd";
227		- status = "disabled";
228		-
229		- ports {
230		- #address-cells = <1>;
231		- #size-cells = <0>;
232		-
233		- tcon0_in: port@0 {
234		- #address-cells = <1>;
235		- #size-cells = <0>;
236		- reg = <0>;
237		-
238		- tcon0_in_drc0: endpoint@0 {
239		- reg = <0>;
240		- remote-endpoint = <&drc0_out_tcon0>;
241		- };
242		- };
243		-
244		- tcon0_out: port@1 {
245		- #address-cells = <1>;
246		- #size-cells = <0>;
247		- reg = <1>;
248		-
249		- tcon0_out_dsi: endpoint@1 {
250		- reg = <1>;
251		- remote-endpoint = <&dsi_in_tcon0>;
252		- };
253		- };
254		- };
	205	+ soc {
	206	+ video-codec@1c0e000 {
	207	+ compatible = "allwinner,sun8i-a33-video-engine";
	208	+ reg = <0x01c0e000 0x1000>;
	209	+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
	210	+ <&ccu CLK_DRAM_VE>;
	211	+ clock-names = "ahb", "mod", "ram";
	212	+ resets = <&ccu RST_BUS_VE>;
	213	+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	214	+ allwinner,sram = <&ve_sram 1>;
255	215	};
256	216
257	217	crypto: crypto-engine@1c15000 {
258		- compatible = "allwinner,sun4i-a10-crypto";
	218	+ compatible = "allwinner,sun8i-a33-crypto";
259	219	reg = <0x01c15000 0x1000>;
260	220	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
261	221	clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
..	..	@@ -305,19 +265,12 @@
305	265	phys = <&dphy>;
306	266	phy-names = "dphy";
307	267	status = "disabled";
	268	+ #address-cells = <1>;
	269	+ #size-cells = <0>;
308	270
309		- ports {
310		- #address-cells = <1>;
311		- #size-cells = <0>;
312		-
313		- port@0 {
314		- #address-cells = <1>;
315		- #size-cells = <0>;
316		- reg = <0>;
317		-
318		- dsi_in_tcon0: endpoint {
319		- remote-endpoint = <&tcon0_out_dsi>;
320		- };
	271	+ port {
	272	+ dsi_in_tcon0: endpoint {
	273	+ remote-endpoint = <&tcon0_out_dsi>;
321	274	};
322	275	};
323	276	};
..	..	@@ -332,115 +285,6 @@
332	285	status = "disabled";
333	286	#phy-cells = <0>;
334	287	};
335		-
336		- fe0: display-frontend@1e00000 {
337		- compatible = "allwinner,sun8i-a33-display-frontend";
338		- reg = <0x01e00000 0x20000>;
339		- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
340		- clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
341		- <&ccu CLK_DRAM_DE_FE>;
342		- clock-names = "ahb", "mod",
343		- "ram";
344		- resets = <&ccu RST_BUS_DE_FE>;
345		-
346		- ports {
347		- #address-cells = <1>;
348		- #size-cells = <0>;
349		-
350		- fe0_out: port@1 {
351		- #address-cells = <1>;
352		- #size-cells = <0>;
353		- reg = <1>;
354		-
355		- fe0_out_be0: endpoint@0 {
356		- reg = <0>;
357		- remote-endpoint = <&be0_in_fe0>;
358		- };
359		- };
360		- };
361		- };
362		-
363		- be0: display-backend@1e60000 {
364		- compatible = "allwinner,sun8i-a33-display-backend";
365		- reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
366		- reg-names = "be", "sat";
367		- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
368		- clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
369		- <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
370		- clock-names = "ahb", "mod",
371		- "ram", "sat";
372		- resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
373		- reset-names = "be", "sat";
374		- assigned-clocks = <&ccu CLK_DE_BE>;
375		- assigned-clock-rates = <300000000>;
376		-
377		- ports {
378		- #address-cells = <1>;
379		- #size-cells = <0>;
380		-
381		- be0_in: port@0 {
382		- #address-cells = <1>;
383		- #size-cells = <0>;
384		- reg = <0>;
385		-
386		- be0_in_fe0: endpoint@0 {
387		- reg = <0>;
388		- remote-endpoint = <&fe0_out_be0>;
389		- };
390		- };
391		-
392		- be0_out: port@1 {
393		- #address-cells = <1>;
394		- #size-cells = <0>;
395		- reg = <1>;
396		-
397		- be0_out_drc0: endpoint@0 {
398		- reg = <0>;
399		- remote-endpoint = <&drc0_in_be0>;
400		- };
401		- };
402		- };
403		- };
404		-
405		- drc0: drc@1e70000 {
406		- compatible = "allwinner,sun8i-a33-drc";
407		- reg = <0x01e70000 0x10000>;
408		- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
409		- clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
410		- <&ccu CLK_DRAM_DRC>;
411		- clock-names = "ahb", "mod", "ram";
412		- resets = <&ccu RST_BUS_DRC>;
413		-
414		- assigned-clocks = <&ccu CLK_DRC>;
415		- assigned-clock-rates = <300000000>;
416		-
417		- ports {
418		- #address-cells = <1>;
419		- #size-cells = <0>;
420		-
421		- drc0_in: port@0 {
422		- #address-cells = <1>;
423		- #size-cells = <0>;
424		- reg = <0>;
425		-
426		- drc0_in_be0: endpoint@0 {
427		- reg = <0>;
428		- remote-endpoint = <&be0_out_drc0>;
429		- };
430		- };
431		-
432		- drc0_out: port@1 {
433		- #address-cells = <1>;
434		- #size-cells = <0>;
435		- reg = <1>;
436		-
437		- drc0_out_tcon0: endpoint@0 {
438		- reg = <0>;
439		- remote-endpoint = <&tcon0_in_drc0>;
440		- };
441		- };
442		- };
443		- };
444	288	};
445	289
446	290	thermal-zones {
..	..	@@ -453,11 +297,17 @@
453	297	cooling-maps {
454	298	map0 {
455	299	trip = <&cpu_alert0>;
456		- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	300	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	301	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	302	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	303	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
457	304	};
458	305	map1 {
459	306	trip = <&cpu_alert1>;
460		- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	307	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	308	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	309	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	310	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
461	311	};
462	312
463	313	map2 {
..	..	@@ -511,8 +361,33 @@
511	361	};
512	362	};
513	363
	364	+&be0 {
	365	+ compatible = "allwinner,sun8i-a33-display-backend";
	366	+ /* A33 has an extra "SAT" module packed inside the display backend */
	367	+ reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
	368	+ reg-names = "be", "sat";
	369	+ clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
	370	+ <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
	371	+ clock-names = "ahb", "mod",
	372	+ "ram", "sat";
	373	+ resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
	374	+ reset-names = "be", "sat";
	375	+};
	376	+
514	377	&ccu {
515	378	compatible = "allwinner,sun8i-a33-ccu";
	379	+};
	380	+
	381	+&de {
	382	+ compatible = "allwinner,sun8i-a33-display-engine";
	383	+};
	384	+
	385	+&drc0 {
	386	+ compatible = "allwinner,sun8i-a33-drc";
	387	+};
	388	+
	389	+&fe0 {
	390	+ compatible = "allwinner,sun8i-a33-display-frontend";
516	391	};
517	392
518	393	&mali {
..	..	@@ -524,13 +399,27 @@
524	399	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
525	400	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
526	401
527		- uart0_pins_b: uart0@1 {
	402	+ uart0_pb_pins: uart0-pb-pins {
528	403	pins = "PB0", "PB1";
529	404	function = "uart0";
530	405	};
531	406
532	407	};
533	408
	409	+&tcon0 {
	410	+ compatible = "allwinner,sun8i-a33-tcon";
	411	+};
	412	+
	413	+&tcon0_out {
	414	+ #address-cells = <1>;
	415	+ #size-cells = <0>;
	416	+
	417	+ tcon0_out_dsi: endpoint@1 {
	418	+ reg = <1>;
	419	+ remote-endpoint = <&dsi_in_tcon0>;
	420	+ };
	421	+};
	422	+
534	423	&usb_otg {
535	424	compatible = "allwinner,sun8i-a33-musb";
536	425	};