disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/rk312x.dtsi
..
..
@@ -57,9 +57,6 @@
57
57
 
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 	aliases {
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 		ethernet0 = &gmac;
60
-		serial0 = &uart0;
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-		serial1 = &uart1;
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-		serial2 = &uart2;
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 		i2c0 = &i2c0;
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 		i2c1 = &i2c1;
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 		i2c2 = &i2c2;
..
..
@@ -67,6 +64,10 @@
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64
 		mmc0 = &sdmmc;
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 		mmc1 = &sdio;
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 		mmc2 = &emmc;
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+		serial0 = &uart0;
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+		serial1 = &uart1;
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+		serial2 = &uart2;
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+		spi0 = &spi0;
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 	};
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72
 
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 	cpus {
..
..
@@ -113,8 +114,8 @@
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 		clocks = <&cru PLL_APLL>;
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 		rockchip,leakage-voltage-sel = <
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 			1   13   0
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-			14  18   1
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-			18  254  2
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+			14  49   1
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+			50  254  2
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 		>;
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 		nvmem-cells = <&cpu_leakage>;
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 		nvmem-cell-names = "cpu_leakage";
..
..
@@ -233,7 +234,7 @@
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 		system-status-freq = <
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 			/*system status		freq(KHz)*/
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 			SYS_STATUS_NORMAL	456000
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-			SYS_STATUS_SUSPEND	456000
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+			SYS_STATUS_SUSPEND	300000
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 			SYS_STATUS_REBOOT	456000
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 		>;
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 		auto-min-freq = <456000>;
..
..
@@ -247,6 +248,7 @@
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 		opp-200000000 {
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 			opp-hz = /bits/ 64 <200000000>;
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 			opp-microvolt = <1025000>;
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+			status = "disabled";
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 		};
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 		opp-300000000 {
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 			opp-hz = /bits/ 64 <300000000>;
..
..
@@ -615,7 +617,6 @@
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 		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
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 		clock-names = "aclk_rga", "hclk_rga", "sclk_rga";
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 		power-domains = <&power RK3128_PD_VIO>;
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-		dma-coherent;
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 		status = "disabled";
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 	};
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622
 
..
..
@@ -670,12 +671,12 @@
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 		compatible = "rockchip,rk3128-mipi-dsi";
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 		reg = <0x10110000 0x4000>;
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 		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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-		clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>;
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-		clock-names = "pclk", "h2p", "hs_clk";
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+		clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>;
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+		clock-names = "pclk", "hclk";
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 		resets = <&cru SRST_VIO_MIPI_DSI>;
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 		reset-names = "apb";
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 		phys = <&video_phy>;
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-		phy-names = "mipi_dphy";
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+		phy-names = "dphy";
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 		power-domains = <&power RK3128_PD_VIO>;
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 		rockchip,grf = <&grf>;
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 		#address-cells = <1>;
..
..
@@ -831,12 +832,11 @@
831
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 		#size-cells = <0>;
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 		pinctrl-names = "default";
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 		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
834
-		clock-freq-min-max = <400000 50000000>;
835
-		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
836
-		clock-names = "biu", "ciu";
835
+		max-frequency = <50000000>;
836
+		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
837
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
837
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 		dmas = <&pdma 10>;
838
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 		dma-names = "rx-tx";
839
-		num-slots = <1>;
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 		fifo-depth = <0x100>;
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 		bus-width = <4>;
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 		status = "disabled";
..
..
@@ -996,14 +996,15 @@
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 	};
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997
 
998
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 	video_phy: video-phy@20038000 {
999
-		compatible = "rockchip,rk3128-video-phy";
999
+		compatible = "rockchip,rk3128-dsi-dphy", "rockchip,rk3128-video-phy";
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 		reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
1001
+		reg-names = "phy", "host";
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 		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>,
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 			 <&cru PCLK_MIPI>;
1003
-		clock-names = "ref", "pclk_phy", "pclk_host";
1004
+		clock-names = "ref", "pclk", "pclk_host";
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 		#clock-cells = <0>;
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 		resets = <&cru SRST_MIPIPHY_P>;
1006
-		reset-names = "rst";
1007
+		reset-names = "apb";
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 		power-domains = <&power RK3128_PD_VIO>;
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 		#phy-cells = <0>;
1009
1010
 		status = "disabled";
..
..
@@ -1180,7 +1181,7 @@
1180
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 		reg = <0x20074000 0x1000>;
1181
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 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1182
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 		pinctrl-names = "default";
1183
-		pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
1184
+		pinctrl-0 = <&spi0m0_tx &spi0m0_rx &spi0m0_clk &spi0m0_cs0 &spi0m0_cs1>;
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 		clock-names = "spiclk", "apb_pclk";
1185
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 		dmas = <&pdma 8>, <&pdma 9>;
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 		dma-names = "tx", "rx";
..
..
@@ -1464,6 +1465,10 @@
1464
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 				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1465
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 			};
1466
1467
 
1468
+			sdmmc_det: sdmmc-det {
1469
+				rockchip,pins = <1 RK_PC1 1 &pcfg_pull_none>;
1470
+			};
1471
+
1467
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 			sdmmc_cmd: sdmmc-cmd {
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 				rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
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 			};
..
..
@@ -1603,60 +1608,60 @@
1603
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 			};
1604
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 		};
1605
1610
 
1606
-		spi {
1607
-			spi0_clk: spi0-clk {
1611
+		spi0 {
1612
+			spi0m0_clk: spi0m0-clk {
1608
1613
 				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1609
1614
 			};
1610
1615
 
1611
-			spi0_cs0: spi0-cs0 {
1616
+			spi0m0_cs0: spi0m0-cs0 {
1612
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 				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1613
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 			};
1614
1619
 
1615
-			spi0_tx: spi0-tx {
1620
+			spi0m0_tx: spi0m0-tx {
1616
1621
 				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
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1622
 			};
1618
1623
 
1619
-			spi0_rx: spi0-rx {
1624
+			spi0m0_rx: spi0m0-rx {
1620
1625
 				rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
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 			};
1622
1627
 
1623
-			spi0_cs1: spi0-cs1 {
1628
+			spi0m0_cs1: spi0m0-cs1 {
1624
1629
 				rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
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1630
 			};
1626
1631
 
1627
-			spi1_clk: spi1-clk {
1632
+			spi0m1_clk: spi0m1-clk {
1628
1633
 				rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
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1634
 			};
1630
1635
 
1631
-			spi1_cs0: spi1-cs0 {
1636
+			spi0m1_cs0: spi0m1-cs0 {
1632
1637
 				rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1633
1638
 			};
1634
1639
 
1635
-			spi1_tx: spi1-tx {
1640
+			spi0m1_tx: spi0m1-tx {
1636
1641
 				rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1637
1642
 			};
1638
1643
 
1639
-			spi1_rx: spi1-rx {
1644
+			spi0m1_rx: spi0m1-rx {
1640
1645
 				rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1641
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 			};
1642
1647
 
1643
-			spi1_cs1: spi1-cs1 {
1648
+			spi0m1_cs1: spi0m1-cs1 {
1644
1649
 				rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1645
1650
 			};
1646
1651
 
1647
-			spi2_clk: spi2-clk {
1652
+			spi0m2_clk: spi0m2-clk {
1648
1653
 				rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1649
1654
 			};
1650
1655
 
1651
-			spi2_cs0: spi2-cs0 {
1656
+			spi0m2_cs0: spi0m2-cs0 {
1652
1657
 				rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1653
1658
 			};
1654
1659
 
1655
-			spi2_tx: spi2-tx {
1660
+			spi0m2_tx: spi0m2-tx {
1656
1661
 				rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1657
1662
 			};
1658
1663
 
1659
-			spi2_rx: spi2-rx {
1664
+			spi0m2_rx: spi0m2-rx {
1660
1665
 				rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
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 			};
1662
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 		};