disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/r8a7778.dtsi
..
..
@@ -1,6 +1,6 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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- * Device Tree Source for Renesas r8a7778
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+ * Device Tree Source for the R-Car M1A (R8A77781) SoC
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  *
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  * Copyright (C) 2013  Renesas Solutions Corp.
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  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
..
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@@ -78,11 +78,12 @@
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 			<0xfe780010 4>,
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 			<0xfe780024 4>,
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 			<0xfe780044 4>,
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-			<0xfe780064 4>;
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-		interrupts =   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
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-				GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
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-				GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
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-				GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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+			<0xfe780064 4>,
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+			<0xfe780000 4>;
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+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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 		sense-bitfield-width = <2>;
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 	};
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..
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@@ -141,7 +142,7 @@
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 		interrupt-controller;
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 	};
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-	pfc: pin-controller@fffc0000 {
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+	pfc: pinctrl@fffc0000 {
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 		compatible = "renesas,pfc-r8a7778";
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 		reg = <0xfffc0000 0x118>;
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 	};
..
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@@ -367,6 +368,30 @@
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 		status = "disabled";
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 	};
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+	hscif0: serial@ffe48000 {
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+		compatible = "renesas,hscif-r8a7778",
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+			     "renesas,rcar-gen1-hscif", "renesas,hscif";
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+		reg = <0xffe48000 96>;
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+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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+		clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
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+			 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
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+		clock-names = "fck", "brg_int", "scif_clk";
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+		power-domains = <&cpg_clocks>;
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+		status = "disabled";
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+	};
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+
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+	hscif1: serial@ffe49000 {
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+		compatible = "renesas,hscif-r8a7778",
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+			     "renesas,rcar-gen1-hscif", "renesas,hscif";
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+		reg = <0xffe49000 96>;
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+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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+		clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
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+			 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
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+		clock-names = "fck", "brg_int", "scif_clk";
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+		power-domains = <&cpg_clocks>;
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+		status = "disabled";
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+	};
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+
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 	mmcif: mmc@ffe4e000 {
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 		compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
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 		reg = <0xffe4e000 0x100>;
..
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@@ -376,7 +401,7 @@
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 		status = "disabled";
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 	};
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-	sdhi0: sd@ffe4c000 {
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+	sdhi0: mmc@ffe4c000 {
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 		compatible = "renesas,sdhi-r8a7778",
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 			     "renesas,rcar-gen1-sdhi";
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 		reg = <0xffe4c000 0x100>;
..
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@@ -386,7 +411,7 @@
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 		status = "disabled";
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 	};
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-	sdhi1: sd@ffe4d000 {
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+	sdhi1: mmc@ffe4d000 {
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 		compatible = "renesas,sdhi-r8a7778",
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 			     "renesas,rcar-gen1-sdhi";
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 		reg = <0xffe4d000 0x100>;
..
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@@ -396,7 +421,7 @@
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 		status = "disabled";
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 	};
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-	sdhi2: sd@ffe4f000 {
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+	sdhi2: mmc@ffe4f000 {
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 		compatible = "renesas,sdhi-r8a7778",
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 			     "renesas,rcar-gen1-sdhi";
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 		reg = <0xffe4f000 0x100>;
..
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@@ -474,14 +499,17 @@
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 		audio_clk_a: audio_clk_a {
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 			compatible = "fixed-clock";
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 			#clock-cells = <0>;
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+			clock-frequency = <0>;
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 		};
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 		audio_clk_b: audio_clk_b {
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 			compatible = "fixed-clock";
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 			#clock-cells = <0>;
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+			clock-frequency = <0>;
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 		};
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 		audio_clk_c: audio_clk_c {
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 			compatible = "fixed-clock";
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 			#clock-cells = <0>;
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+			clock-frequency = <0>;
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 		};
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 		/* Fixed ratio clocks */
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@@ -535,6 +563,8 @@
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 				 <&cpg_clocks R8A7778_CLK_P>,
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 				 <&cpg_clocks R8A7778_CLK_P>,
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 				 <&cpg_clocks R8A7778_CLK_P>,
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+				 <&cpg_clocks R8A7778_CLK_S>,
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+				 <&cpg_clocks R8A7778_CLK_S>,
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 				 <&cpg_clocks R8A7778_CLK_P>,
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 				 <&cpg_clocks R8A7778_CLK_P>,
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 				 <&cpg_clocks R8A7778_CLK_P>,
..
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@@ -551,6 +581,7 @@
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 				R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
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 				R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
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 				R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
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+				R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
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 				R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
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 				R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
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 				R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
..
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@@ -560,6 +591,7 @@
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 			clock-output-names =
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 				"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
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 				"scif1", "scif2", "scif3", "scif4", "scif5",
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+				"hscif0", "hscif1",
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 				"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
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 				"ssi2", "ssi3", "sru", "hspi";
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 		};