disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/r7s72100.dtsi
..
..
@@ -313,9 +313,9 @@
313
313
 		mmcif: mmc@e804c800 {
314
314
 			compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
315
315
 			reg = <0xe804c800 0x80>;
316
-			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
317
-				      GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
318
-				      GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
316
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
317
+				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
318
+				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
319
319
 			clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
320
320
 			power-domains = <&cpg_clocks>;
321
321
 			reg-io-width = <4>;
..
..
@@ -323,12 +323,12 @@
323
323
 			status = "disabled";
324
324
 		};
325
325
 
326
-		sdhi0: sd@e804e000 {
326
+		sdhi0: mmc@e804e000 {
327
327
 			compatible = "renesas,sdhi-r7s72100";
328
328
 			reg = <0xe804e000 0x100>;
329
-			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
330
-				      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
331
-				      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
329
+			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
330
+				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
331
+				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
332
332
 
333
333
 			clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
334
334
 				 <&mstp12_clks R7S72100_CLK_SDHI01>;
..
..
@@ -339,12 +339,12 @@
339
339
 			status = "disabled";
340
340
 		};
341
341
 
342
-		sdhi1: sd@e804e800 {
342
+		sdhi1: mmc@e804e800 {
343
343
 			compatible = "renesas,sdhi-r7s72100";
344
344
 			reg = <0xe804e800 0x100>;
345
-			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
346
-				      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
347
-				      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
345
+			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
346
+				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
347
+				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
348
348
 
349
349
 			clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
350
350
 				 <&mstp12_clks R7S72100_CLK_SDHI11>;
..
..
@@ -467,11 +467,12 @@
467
467
 			#clock-cells = <1>;
468
468
 			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
469
469
 			reg = <0xfcfe0438 4>;
470
-			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
470
+			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
471
471
 			clock-indices = <
472
472
 				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
473
+				R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
473
474
 			>;
474
-			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
475
+			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
475
476
 		};
476
477
 
477
478
 		mstp10_clks: mstp10_clks@fcfe043c {
..
..
@@ -498,7 +499,7 @@
498
499
 			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
499
500
 		};
500
501
 
501
-		pinctrl: pin-controller@fcfe3000 {
502
+		pinctrl: pinctrl@fcfe3000 {
502
503
 			compatible = "renesas,r7s72100-ports";
503
504
 
504
505
 			reg = <0xfcfe3000 0x4230>;
..
..
@@ -670,6 +671,25 @@
670
671
 			status = "disabled";
671
672
 		};
672
673
 
674
+		irqc: interrupt-controller@fcfef800 {
675
+			compatible = "renesas,r7s72100-irqc",
676
+				     "renesas,rza1-irqc";
677
+			#interrupt-cells = <2>;
678
+			#address-cells = <0>;
679
+			interrupt-controller;
680
+			reg = <0xfcfef800 0x6>;
681
+			interrupt-map =
682
+				<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
683
+				<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
684
+				<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
685
+				<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
686
+				<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
687
+				<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
688
+				<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
689
+				<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
690
+			interrupt-map-mask = <7 0>;
691
+		};
692
+
673
693
 		mtu2: timer@fcff0000 {
674
694
 			compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
675
695
 			reg = <0xfcff0000 0x400>;