disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/omap36xx.dtsi
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@@ -1,7 +1,7 @@
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 /*
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  * Device Tree Source for OMAP3 SoC
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  *
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- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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  *
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  * This file is licensed under the terms of the GNU General Public License
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  * version 2.  This program is licensed "as is" without any warranty of any
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@@ -19,16 +19,66 @@
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 	};
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 	cpus {
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-		/* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
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+		/* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
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 		cpu: cpu@0 {
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-			operating-points = <
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-				/* kHz    uV */
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-				300000  1012500
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-				600000  1200000
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-				800000  1325000
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-			>;
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-			clock-latency = <300000>; /* From legacy driver */
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+			operating-points-v2 = <&cpu0_opp_table>;
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+
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+			vbb-supply = <&abb_mpu_iva>;
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+			clock-latency = <300000>; /* From omap-cpufreq driver */
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+			#cooling-cells = <2>;
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 		};
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+	};
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+
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+	/* see Documentation/devicetree/bindings/opp/opp.txt */
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+	cpu0_opp_table: opp-table {
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+		compatible = "operating-points-v2-ti-cpu";
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+		syscon = <&scm_conf>;
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+
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+		opp50-300000000 {
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+			opp-hz = /bits/ 64 <300000000>;
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+			/*
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+			 * we currently only select the max voltage from table
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+			 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
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+			 * Format is:	cpu0-supply:	<target min max>
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+			 *		vbb-supply:	<target min max>
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+			 */
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+			opp-microvolt = <1012500 1012500 1012500>,
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+					 <1012500 1012500 1012500>;
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+			/*
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+			 * first value is silicon revision bit mask
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+			 * second one is "speed binned" bit mask
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+			 */
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+			opp-supported-hw = <0xffffffff 3>;
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+			opp-suspend;
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+		};
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+
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+		opp100-600000000 {
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+			opp-hz = /bits/ 64 <600000000>;
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+			opp-microvolt = <1200000 1200000 1200000>,
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+					 <1200000 1200000 1200000>;
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+			opp-supported-hw = <0xffffffff 3>;
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+		};
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+
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+		opp130-800000000 {
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+			opp-hz = /bits/ 64 <800000000>;
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+			opp-microvolt = <1325000 1325000 1325000>,
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+					 <1325000 1325000 1325000>;
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+			opp-supported-hw = <0xffffffff 3>;
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+		};
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+
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+		opp1g-1000000000 {
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+			opp-hz = /bits/ 64 <1000000000>;
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+			opp-microvolt = <1375000 1375000 1375000>,
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+					 <1375000 1375000 1375000>;
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+			/* only on am/dm37x with speed-binned bit set */
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+			opp-supported-hw = <0xffffffff 2>;
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+			turbo-mode;
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+		};
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+	};
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+
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+	opp_supply_mpu_iva: opp_supply {
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+		compatible = "ti,omap-opp-supply";
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+		ti,absolute-max-voltage-uv = <1375000>;
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 	};
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 	ocp@68000000 {
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@@ -139,11 +189,43 @@
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 				interrupts = <18>;
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 			};
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 		};
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+
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+		/*
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+		 * Note that the sysconfig register layout is a subset of the
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+		 * "ti,sysc-omap4" type register with just sidle and midle bits
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+		 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
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+		 */
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+		sgx_module: target-module@50000000 {
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+			compatible = "ti,sysc-omap4", "ti,sysc";
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+			reg = <0x5000fe00 0x4>,
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+			      <0x5000fe10 0x4>;
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+			reg-names = "rev", "sysc";
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+			ti,sysc-midle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_NO>,
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+					<SYSC_IDLE_SMART>;
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_NO>,
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+					<SYSC_IDLE_SMART>;
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+			clocks = <&sgx_fck>, <&sgx_ick>;
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+			clock-names = "fck", "ick";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0 0x50000000 0x2000000>;
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+
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+			/*
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+			 * Closed source PowerVR driver, no child device
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+			 * binding or driver in mainline
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+			 */
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+		};
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 	};
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 	thermal_zones: thermal-zones {
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 		#include "omap3-cpu-thermal.dtsi"
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 	};
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+};
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+
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+&sdma {
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+	compatible = "ti,omap3630-sdma", "ti,omap-sdma";
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 };
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 /* OMAP3630 needs dss_96m_fck for VENC */
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@@ -153,7 +235,7 @@
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 };
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 &ssi {
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-	status = "ok";
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+	status = "okay";
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 	clocks = <&ssi_ssr_fck>,
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 		 <&ssi_sst_fck>,