disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/omap34xx.dtsi
..
..
@@ -1,7 +1,7 @@
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 /*
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  * Device Tree Source for OMAP34xx/OMAP35xx SoC
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  *
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- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
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  *
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  * This file is licensed under the terms of the GNU General Public License
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  * version 2.  This program is licensed "as is" without any warranty of any
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@@ -16,16 +16,65 @@
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 / {
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 	cpus {
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 		cpu: cpu@0 {
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-			/* OMAP343x/OMAP35xx variants OPP1-5 */
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-			operating-points = <
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-				/* kHz    uV */
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-				125000   975000
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-				250000  1075000
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-				500000  1200000
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-				550000  1270000
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-				600000  1350000
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-			>;
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+			/* OMAP343x/OMAP35xx variants OPP1-6 */
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+			operating-points-v2 = <&cpu0_opp_table>;
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+
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 			clock-latency = <300000>; /* From legacy driver */
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+			#cooling-cells = <2>;
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+		};
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+	};
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+
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+	/* see Documentation/devicetree/bindings/opp/opp.txt */
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+	cpu0_opp_table: opp-table {
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+		compatible = "operating-points-v2-ti-cpu";
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+		syscon = <&scm_conf>;
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+
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+		opp1-125000000 {
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+			opp-hz = /bits/ 64 <125000000>;
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+			/*
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+			 * we currently only select the max voltage from table
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+			 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
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+			 * Format is: <target min max>
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+			 */
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+			opp-microvolt = <975000 975000 975000>;
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+			/*
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+			 * first value is silicon revision bit mask
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+			 * second one 720MHz Device Identification bit mask
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+			 */
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+			opp-supported-hw = <0xffffffff 3>;
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+		};
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+
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+		opp2-250000000 {
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+			opp-hz = /bits/ 64 <250000000>;
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+			opp-microvolt = <1075000 1075000 1075000>;
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+			opp-supported-hw = <0xffffffff 3>;
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+			opp-suspend;
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+		};
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+
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+		opp3-500000000 {
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+			opp-hz = /bits/ 64 <500000000>;
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+			opp-microvolt = <1200000 1200000 1200000>;
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+			opp-supported-hw = <0xffffffff 3>;
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+		};
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+
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+		opp4-550000000 {
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+			opp-hz = /bits/ 64 <550000000>;
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+			opp-microvolt = <1275000 1275000 1275000>;
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+			opp-supported-hw = <0xffffffff 3>;
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+		};
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+
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+		opp5-600000000 {
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+			opp-hz = /bits/ 64 <600000000>;
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+			opp-microvolt = <1350000 1350000 1350000>;
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+			opp-supported-hw = <0xffffffff 3>;
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+		};
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+
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+		opp6-720000000 {
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+			opp-hz = /bits/ 64 <720000000>;
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+			opp-microvolt = <1350000 1350000 1350000>;
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+			/* only high-speed grade omap3530 devices */
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+			opp-supported-hw = <0xffffffff 2>;
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+			turbo-mode;
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 		};
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 	};
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..
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@@ -100,6 +149,32 @@
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 				interrupts = <18>;
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 			};
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 		};
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+
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+		/*
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+		 * On omap34xx the OCP registers do not seem to be accessible
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+		 * at all unlike on 36xx. Maybe SGX is permanently set to
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+		 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
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+		 * write-only at 0x50000e10. We detect SGX based on the SGX
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+		 * revision register instead of the unreadable OCP revision
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+		 * register. Also note that on early 34xx es1 revision there
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+		 * are also different clocks, but we do not have any dts users
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+		 * for it.
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+		 */
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+		sgx_module: target-module@50000000 {
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+			compatible = "ti,sysc-omap2", "ti,sysc";
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+			reg = <0x50000014 0x4>;
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+			reg-names = "rev";
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+			clocks = <&sgx_fck>, <&sgx_ick>;
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+			clock-names = "fck", "ick";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0 0x50000000 0x4000>;
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+
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+			/*
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+			 * Closed source PowerVR driver, no child device
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+			 * binding or driver in mainline
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+			 */
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+		};
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 	};
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 	thermal_zones: thermal-zones {
..
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@@ -108,7 +183,7 @@
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 };
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 &ssi {
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-	status = "ok";
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+	status = "okay";
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 	clocks = <&ssi_ssr_fck>,
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 		 <&ssi_sst_fck>,