disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/mt2701.dtsi
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@@ -12,10 +12,11 @@
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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 #include <dt-bindings/memory/mt2701-larb-port.h>
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 #include <dt-bindings/reset/mt2701-resets.h>
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-#include "skeleton64.dtsi"
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 #include "mt2701-pinfunc.h"
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 / {
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+	#address-cells = <2>;
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+	#size-cells = <2>;
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 	compatible = "mediatek,mt2701";
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 	interrupt-parent = <&cirq>;
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..
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@@ -147,7 +148,7 @@
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 		reg = <0 0x10005000 0 0x1000>;
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 	};
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-	scpsys: scpsys@10006000 {
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+	scpsys: power-controller@10006000 {
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 		compatible = "mediatek,mt2701-scpsys", "syscon";
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 		#power-domain-cells = <1>;
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 		reg = <0 0x10006000 0 0x1000>;
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@@ -568,6 +569,19 @@
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 			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
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 	};
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+	jpegenc: jpegenc@1500a000 {
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+		compatible = "mediatek,mt2701-jpgenc",
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+			     "mediatek,mtk-jpgenc";
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+		reg = <0 0x1500a000 0 0x1000>;
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+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
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+		clocks =  <&imgsys CLK_IMG_VENC>;
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+		clock-names = "jpgenc";
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+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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+		mediatek,larb = <&larb2>;
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+		iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
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+			 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
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+	};
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+
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 	vdecsys: syscon@16000000 {
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 		compatible = "mediatek,mt2701-vdecsys", "syscon";
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 		reg = <0 0x16000000 0 0x1000>;
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@@ -670,6 +684,39 @@
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 		};
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 	};
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+	usb2: usb@11200000 {
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+		compatible = "mediatek,mt2701-musb",
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+			     "mediatek,mtk-musb";
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+		reg = <0 0x11200000 0 0x1000>;
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+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
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+		interrupt-names = "mc";
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+		phys = <&u2port2 PHY_TYPE_USB2>;
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+		dr_mode = "otg";
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+		clocks = <&pericfg CLK_PERI_USB0>,
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+			 <&pericfg CLK_PERI_USB0_MCU>,
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+			 <&pericfg CLK_PERI_USB_SLV>;
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+		clock-names = "main","mcu","univpll";
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+		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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+		status = "disabled";
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+	};
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+
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+	u2phy0: usb-phy@11210000 {
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+		compatible = "mediatek,generic-tphy-v1";
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+		reg = <0 0x11210000 0 0x0800>;
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+		#address-cells = <2>;
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+		#size-cells = <2>;
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+		ranges;
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+		status = "okay";
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+
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+		u2port2: usb-phy@1a1c4800 {
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+			reg = <0 0x11210800 0 0x0100>;
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+			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
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+			clock-names = "ref";
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+			#phy-cells = <1>;
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+			status = "okay";
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+		};
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+	};
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+
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 	ethsys: syscon@1b000000 {
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 		compatible = "mediatek,mt2701-ethsys", "syscon";
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 		reg = <0 0x1b000000 0 0x1000>;