~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,51 +1,13 @@
	1	+// SPDX-License-Identifier: GPL-2.0 OR MIT
1	2	/*
2	3	* Copyright 2015 Endless Mobile, Inc.
3	4	* Author: Carlo Caione <carlo@endlessm.com>
4		- *
5		- * This file is dual-licensed: you can use it either under the terms
6		- * of the GPL or the X11 license, at your option. Note that this dual
7		- * licensing only applies to this file, and not this project as a
8		- * whole.
9		- *
10		- * a) This library is free software; you can redistribute it and/or
11		- * modify it under the terms of the GNU General Public License as
12		- * published by the Free Software Foundation; either version 2 of the
13		- * License, or (at your option) any later version.
14		- *
15		- * This library is distributed in the hope that it will be useful,
16		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
17		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18		- * GNU General Public License for more details.
19		- *
20		- * You should have received a copy of the GNU General Public License
21		- * along with this program. If not, see <http://www.gnu.org/licenses/>.
22		- *
23		- * Or, alternatively,
24		- *
25		- * b) Permission is hereby granted, free of charge, to any person
26		- * obtaining a copy of this software and associated documentation
27		- * files (the "Software"), to deal in the Software without
28		- * restriction, including without limitation the rights to use,
29		- * copy, modify, merge, publish, distribute, sublicense, and/or
30		- * sell copies of the Software, and to permit persons to whom the
31		- * Software is furnished to do so, subject to the following
32		- * conditions:
33		- *
34		- * The above copyright notice and this permission notice shall be
35		- * included in all copies or substantial portions of the Software.
36		- *
37		- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38		- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39		- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40		- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41		- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42		- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43		- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44		- * OTHER DEALINGS IN THE SOFTWARE.
45	5	*/
46	6
	7	+#include <dt-bindings/clock/meson8-ddr-clkc.h>
47	8	#include <dt-bindings/clock/meson8b-clkc.h>
48	9	#include <dt-bindings/gpio/meson8b-gpio.h>
	10	+#include <dt-bindings/power/meson8-power.h>
49	11	#include <dt-bindings/reset/amlogic,meson8b-reset.h>
50	12	#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
51	13	#include "meson.dtsi"
..	..	@@ -62,6 +24,8 @@
62	24	reg = <0x200>;
63	25	enable-method = "amlogic,meson8b-smp";
64	26	resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
	27	+ operating-points-v2 = <&cpu_opp_table>;
	28	+ clocks = <&clkc CLKID_CPUCLK>;
65	29	};
66	30
67	31	cpu1: cpu@201 {
..	..	@@ -71,6 +35,8 @@
71	35	reg = <0x201>;
72	36	enable-method = "amlogic,meson8b-smp";
73	37	resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
	38	+ operating-points-v2 = <&cpu_opp_table>;
	39	+ clocks = <&clkc CLKID_CPUCLK>;
74	40	};
75	41
76	42	cpu2: cpu@202 {
..	..	@@ -80,6 +46,8 @@
80	46	reg = <0x202>;
81	47	enable-method = "amlogic,meson8b-smp";
82	48	resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
	49	+ operating-points-v2 = <&cpu_opp_table>;
	50	+ clocks = <&clkc CLKID_CPUCLK>;
83	51	};
84	52
85	53	cpu3: cpu@203 {
..	..	@@ -89,6 +57,92 @@
89	57	reg = <0x203>;
90	58	enable-method = "amlogic,meson8b-smp";
91	59	resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
	60	+ operating-points-v2 = <&cpu_opp_table>;
	61	+ clocks = <&clkc CLKID_CPUCLK>;
	62	+ };
	63	+ };
	64	+
	65	+ cpu_opp_table: opp-table {
	66	+ compatible = "operating-points-v2";
	67	+ opp-shared;
	68	+
	69	+ opp-96000000 {
	70	+ opp-hz = /bits/ 64 <96000000>;
	71	+ opp-microvolt = <860000>;
	72	+ };
	73	+ opp-192000000 {
	74	+ opp-hz = /bits/ 64 <192000000>;
	75	+ opp-microvolt = <860000>;
	76	+ };
	77	+ opp-312000000 {
	78	+ opp-hz = /bits/ 64 <312000000>;
	79	+ opp-microvolt = <860000>;
	80	+ };
	81	+ opp-408000000 {
	82	+ opp-hz = /bits/ 64 <408000000>;
	83	+ opp-microvolt = <860000>;
	84	+ };
	85	+ opp-504000000 {
	86	+ opp-hz = /bits/ 64 <504000000>;
	87	+ opp-microvolt = <860000>;
	88	+ };
	89	+ opp-600000000 {
	90	+ opp-hz = /bits/ 64 <600000000>;
	91	+ opp-microvolt = <860000>;
	92	+ };
	93	+ opp-720000000 {
	94	+ opp-hz = /bits/ 64 <720000000>;
	95	+ opp-microvolt = <860000>;
	96	+ };
	97	+ opp-816000000 {
	98	+ opp-hz = /bits/ 64 <816000000>;
	99	+ opp-microvolt = <900000>;
	100	+ };
	101	+ opp-1008000000 {
	102	+ opp-hz = /bits/ 64 <1008000000>;
	103	+ opp-microvolt = <1140000>;
	104	+ };
	105	+ opp-1200000000 {
	106	+ opp-hz = /bits/ 64 <1200000000>;
	107	+ opp-microvolt = <1140000>;
	108	+ };
	109	+ opp-1320000000 {
	110	+ opp-hz = /bits/ 64 <1320000000>;
	111	+ opp-microvolt = <1140000>;
	112	+ };
	113	+ opp-1488000000 {
	114	+ opp-hz = /bits/ 64 <1488000000>;
	115	+ opp-microvolt = <1140000>;
	116	+ };
	117	+ opp-1536000000 {
	118	+ opp-hz = /bits/ 64 <1536000000>;
	119	+ opp-microvolt = <1140000>;
	120	+ };
	121	+ };
	122	+
	123	+ gpu_opp_table: gpu-opp-table {
	124	+ compatible = "operating-points-v2";
	125	+
	126	+ opp-255000000 {
	127	+ opp-hz = /bits/ 64 <255000000>;
	128	+ opp-microvolt = <1100000>;
	129	+ };
	130	+ opp-364285714 {
	131	+ opp-hz = /bits/ 64 <364285714>;
	132	+ opp-microvolt = <1100000>;
	133	+ };
	134	+ opp-425000000 {
	135	+ opp-hz = /bits/ 64 <425000000>;
	136	+ opp-microvolt = <1100000>;
	137	+ };
	138	+ opp-510000000 {
	139	+ opp-hz = /bits/ 64 <510000000>;
	140	+ opp-microvolt = <1100000>;
	141	+ };
	142	+ opp-637500000 {
	143	+ opp-hz = /bits/ 64 <637500000>;
	144	+ opp-microvolt = <1100000>;
	145	+ turbo-mode;
92	146	};
93	147	};
94	148
..	..	@@ -113,9 +167,61 @@
113	167	};
114	168	};
115	169
116		- scu@c4300000 {
117		- compatible = "arm,cortex-a5-scu";
118		- reg = <0xc4300000 0x100>;
	170	+ mmcbus: bus@c8000000 {
	171	+ compatible = "simple-bus";
	172	+ reg = <0xc8000000 0x8000>;
	173	+ #address-cells = <1>;
	174	+ #size-cells = <1>;
	175	+ ranges = <0x0 0xc8000000 0x8000>;
	176	+
	177	+ ddr_clkc: clock-controller@400 {
	178	+ compatible = "amlogic,meson8b-ddr-clkc";
	179	+ reg = <0x400 0x20>;
	180	+ clocks = <&xtal>;
	181	+ clock-names = "xtal";
	182	+ #clock-cells = <1>;
	183	+ };
	184	+
	185	+ dmcbus: bus@6000 {
	186	+ compatible = "simple-bus";
	187	+ reg = <0x6000 0x400>;
	188	+ #address-cells = <1>;
	189	+ #size-cells = <1>;
	190	+ ranges = <0x0 0x6000 0x400>;
	191	+
	192	+ canvas: video-lut@48 {
	193	+ compatible = "amlogic,meson8b-canvas",
	194	+ "amlogic,canvas";
	195	+ reg = <0x48 0x14>;
	196	+ };
	197	+ };
	198	+ };
	199	+
	200	+ apb: bus@d0000000 {
	201	+ compatible = "simple-bus";
	202	+ reg = <0xd0000000 0x200000>;
	203	+ #address-cells = <1>;
	204	+ #size-cells = <1>;
	205	+ ranges = <0x0 0xd0000000 0x200000>;
	206	+
	207	+ mali: gpu@c0000 {
	208	+ compatible = "amlogic,meson8b-mali", "arm,mali-450";
	209	+ reg = <0xc0000 0x40000>;
	210	+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	211	+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	212	+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	213	+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	214	+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	215	+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	216	+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	217	+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
	218	+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
	219	+ "pp0", "ppmmu0", "pp1", "ppmmu1";
	220	+ resets = <&reset RESET_MALI>;
	221	+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
	222	+ clock-names = "bus", "core";
	223	+ operating-points-v2 = <&gpu_opp_table>;
	224	+ };
119	225	};
120	226	}; /* end of / */
121	227
..	..	@@ -146,6 +252,7 @@
146	252	mux {
147	253	groups = "uart_tx_ao_a", "uart_rx_ao_a";
148	254	function = "uart_ao";
	255	+ bias-disable;
149	256	};
150	257	};
151	258
..	..	@@ -153,19 +260,13 @@
153	260	mux {
154	261	groups = "remote_input";
155	262	function = "remote";
	263	+ bias-disable;
156	264	};
157	265	};
158	266	};
159	267	};
160	268
161	269	&cbus {
162		- clkc: clock-controller@4000 {
163		- #clock-cells = <1>;
164		- #reset-cells = <1>;
165		- compatible = "amlogic,meson8b-clkc";
166		- reg = <0x8000 0x4>, <0x4000 0x400>;
167		- };
168		-
169	270	reset: reset-controller@4404 {
170	271	compatible = "amlogic,meson8b-reset";
171	272	reg = <0x4404 0x9c>;
..	..	@@ -182,6 +283,11 @@
182	283	reg = <0x86c0 0x10>;
183	284	#pwm-cells = <3>;
184	285	status = "disabled";
	286	+ };
	287	+
	288	+ clock-measure@8758 {
	289	+ compatible = "amlogic,meson8b-clk-measure";
	290	+ reg = <0x8758 0x1c>;
185	291	};
186	292
187	293	pinctrl_cbus: pinctrl@9880 {
..	..	@@ -220,6 +326,31 @@
220	326	"eth_rxd3",
221	327	"eth_rxd2";
222	328	function = "ethernet";
	329	+ bias-disable;
	330	+ };
	331	+ };
	332	+
	333	+ eth_rmii_pins: eth-rmii {
	334	+ mux {
	335	+ groups = "eth_tx_en",
	336	+ "eth_txd1_0",
	337	+ "eth_txd0_0",
	338	+ "eth_rx_clk",
	339	+ "eth_rx_dv",
	340	+ "eth_rxd1",
	341	+ "eth_rxd0",
	342	+ "eth_mdio_en",
	343	+ "eth_mdc";
	344	+ function = "ethernet";
	345	+ bias-disable;
	346	+ };
	347	+ };
	348	+
	349	+ i2c_a_pins: i2c-a {
	350	+ mux {
	351	+ groups = "i2c_sda_a", "i2c_sck_a";
	352	+ function = "i2c_a";
	353	+ bias-disable;
223	354	};
224	355	};
225	356
..	..	@@ -228,6 +359,51 @@
228	359	groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
229	360	"sd_d3_b", "sd_clk_b", "sd_cmd_b";
230	361	function = "sd_b";
	362	+ bias-disable;
	363	+ };
	364	+ };
	365	+
	366	+ sdxc_c_pins: sdxc-c {
	367	+ mux {
	368	+ groups = "sdxc_d0_c", "sdxc_d13_c",
	369	+ "sdxc_d47_c", "sdxc_clk_c",
	370	+ "sdxc_cmd_c";
	371	+ function = "sdxc_c";
	372	+ bias-pull-up;
	373	+ };
	374	+ };
	375	+
	376	+ pwm_c1_pins: pwm-c1 {
	377	+ mux {
	378	+ groups = "pwm_c1";
	379	+ function = "pwm_c";
	380	+ bias-disable;
	381	+ };
	382	+ };
	383	+
	384	+ pwm_d_pins: pwm-d {
	385	+ mux {
	386	+ groups = "pwm_d";
	387	+ function = "pwm_d";
	388	+ bias-disable;
	389	+ };
	390	+ };
	391	+
	392	+ uart_b0_pins: uart-b0 {
	393	+ mux {
	394	+ groups = "uart_tx_b0",
	395	+ "uart_rx_b0";
	396	+ function = "uart_b";
	397	+ bias-disable;
	398	+ };
	399	+ };
	400	+
	401	+ uart_b0_cts_rts_pins: uart-b0-cts-rts {
	402	+ mux {
	403	+ groups = "uart_cts_b0",
	404	+ "uart_rts_b0";
	405	+ function = "uart_b";
	406	+ bias-disable;
231	407	};
232	408	};
233	409	};
..	..	@@ -245,6 +421,11 @@
245	421	compatible = "amlogic,meson8b-efuse";
246	422	clocks = <&clkc CLKID_EFUSE>;
247	423	clock-names = "core";
	424	+
	425	+ temperature_calib: calib@1f4 {
	426	+ /* only the upper two bytes are relevant */
	427	+ reg = <0x1f4 0x4>;
	428	+ };
248	429	};
249	430
250	431	&ethmac {
..	..	@@ -255,17 +436,56 @@
255	436
256	437	clocks = <&clkc CLKID_ETH>,
257	438	<&clkc CLKID_MPLL2>,
258		- <&clkc CLKID_MPLL2>;
259		- clock-names = "stmmaceth", "clkin0", "clkin1";
	439	+ <&clkc CLKID_MPLL2>,
	440	+ <&clkc CLKID_FCLK_DIV2>;
	441	+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
	442	+ rx-fifo-depth = <4096>;
	443	+ tx-fifo-depth = <2048>;
260	444
261	445	resets = <&reset RESET_ETHERNET>;
262	446	reset-names = "stmmaceth";
	447	+
	448	+ power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
263	449	};
264	450
265	451	&gpio_intc {
266	452	compatible = "amlogic,meson-gpio-intc",
267	453	"amlogic,meson8b-gpio-intc";
268	454	status = "okay";
	455	+};
	456	+
	457	+&hhi {
	458	+ clkc: clock-controller {
	459	+ compatible = "amlogic,meson8b-clkc";
	460	+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
	461	+ clock-names = "xtal", "ddr_pll";
	462	+ #clock-cells = <1>;
	463	+ #reset-cells = <1>;
	464	+ };
	465	+
	466	+ pwrc: power-controller {
	467	+ compatible = "amlogic,meson8b-pwrc";
	468	+ #power-domain-cells = <1>;
	469	+ amlogic,ao-sysctrl = <&pmu>;
	470	+ resets = <&reset RESET_DBLK>,
	471	+ <&reset RESET_PIC_DC>,
	472	+ <&reset RESET_HDMI_APB>,
	473	+ <&reset RESET_HDMI_SYSTEM_RESET>,
	474	+ <&reset RESET_VENCI>,
	475	+ <&reset RESET_VENCP>,
	476	+ <&reset RESET_VDAC_4>,
	477	+ <&reset RESET_VENCL>,
	478	+ <&reset RESET_VIU>,
	479	+ <&reset RESET_VENC>,
	480	+ <&reset RESET_RDMA>;
	481	+ reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
	482	+ "venci", "vencp", "vdac", "vencl", "viu",
	483	+ "venc", "rdma";
	484	+ clocks = <&clkc CLKID_VPU>;
	485	+ clock-names = "vpu";
	486	+ assigned-clocks = <&clkc CLKID_VPU>;
	487	+ assigned-clock-rates = <182142857>;
	488	+ };
269	489	};
270	490
271	491	&hwrng {
..	..	@@ -295,6 +515,33 @@
295	515	arm,shared-override;
296	516	};
297	517
	518	+&periph {
	519	+ scu@0 {
	520	+ compatible = "arm,cortex-a5-scu";
	521	+ reg = <0x0 0x100>;
	522	+ };
	523	+
	524	+ timer@200 {
	525	+ compatible = "arm,cortex-a5-global-timer";
	526	+ reg = <0x200 0x20>;
	527	+ interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
	528	+ clocks = <&clkc CLKID_PERIPH>;
	529	+
	530	+ /*
	531	+ * the arm_global_timer driver currently does not handle clock
	532	+ * rate changes. Keep it disabled for now.
	533	+ */
	534	+ status = "disabled";
	535	+ };
	536	+
	537	+ timer@600 {
	538	+ compatible = "arm,cortex-a5-twd-timer";
	539	+ reg = <0x600 0x20>;
	540	+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
	541	+ clocks = <&clkc CLKID_PERIPH>;
	542	+ };
	543	+};
	544	+
298	545	&pwm_ab {
299	546	compatible = "amlogic,meson8b-pwm";
300	547	};
..	..	@@ -303,11 +550,28 @@
303	550	compatible = "amlogic,meson8b-pwm";
304	551	};
305	552
	553	+&rtc {
	554	+ compatible = "amlogic,meson8b-rtc";
	555	+ resets = <&reset RESET_RTC>;
	556	+};
	557	+
306	558	&saradc {
307	559	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
308		- clocks = <&clkc CLKID_XTAL>,
309		- <&clkc CLKID_SAR_ADC>;
	560	+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
310	561	clock-names = "clkin", "core";
	562	+ amlogic,hhi-sysctrl = <&hhi>;
	563	+ nvmem-cells = <&temperature_calib>;
	564	+ nvmem-cell-names = "temperature_calib";
	565	+};
	566	+
	567	+&sdhc {
	568	+ compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
	569	+ clocks = <&xtal>,
	570	+ <&clkc CLKID_FCLK_DIV4>,
	571	+ <&clkc CLKID_FCLK_DIV3>,
	572	+ <&clkc CLKID_FCLK_DIV5>,
	573	+ <&clkc CLKID_SDHC>;
	574	+ clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
311	575	};
312	576
313	577	&sdio {
..	..	@@ -316,28 +580,33 @@
316	580	clock-names = "core", "clkin";
317	581	};
318	582
	583	+&timer_abcde {
	584	+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
	585	+ clock-names = "xtal", "pclk";
	586	+};
	587	+
319	588	&uart_AO {
320		- compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
321		- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
322		- clock-names = "baud", "xtal", "pclk";
	589	+ compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart";
	590	+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
	591	+ clock-names = "xtal", "pclk", "baud";
323	592	};
324	593
325	594	&uart_A {
326		- compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
327		- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
328		- clock-names = "baud", "xtal", "pclk";
	595	+ compatible = "amlogic,meson8b-uart";
	596	+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
	597	+ clock-names = "xtal", "pclk", "baud";
329	598	};
330	599
331	600	&uart_B {
332		- compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
333		- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
334		- clock-names = "baud", "xtal", "pclk";
	601	+ compatible = "amlogic,meson8b-uart";
	602	+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
	603	+ clock-names = "xtal", "pclk", "baud";
335	604	};
336	605
337	606	&uart_C {
338		- compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
339		- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
340		- clock-names = "baud", "xtal", "pclk";
	607	+ compatible = "amlogic,meson8b-uart";
	608	+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
	609	+ clock-names = "xtal", "pclk", "baud";
341	610	};
342	611
343	612	&usb0 {