forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8 
 kernel/arch/arm/boot/dts/meson8.dtsi
....@@ -1,50 +1,12 @@
1
+// SPDX-License-Identifier: GPL-2.0 OR MIT
12 /*
23  * Copyright 2014 Carlo Caione <carlo@caione.org>
3
- *
4
- * This file is dual-licensed: you can use it either under the terms
5
- * of the GPL or the X11 license, at your option. Note that this dual
6
- * licensing only applies to this file, and not this project as a
7
- * whole.
8
- *
9
- *  a) This library is free software; you can redistribute it and/or
10
- *     modify it under the terms of the GNU General Public License as
11
- *     published by the Free Software Foundation; either version 2 of the
12
- *     License, or (at your option) any later version.
13
- *
14
- *     This library is distributed in the hope that it will be useful,
15
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
- *     GNU General Public License for more details.
18
- *
19
- *     You should have received a copy of the GNU General Public License
20
- *     along with this program. If not, see <http://www.gnu.org/licenses/>.
21
- *
22
- * Or, alternatively,
23
- *
24
- *  b) Permission is hereby granted, free of charge, to any person
25
- *     obtaining a copy of this software and associated documentation
26
- *     files (the "Software"), to deal in the Software without
27
- *     restriction, including without limitation the rights to use,
28
- *     copy, modify, merge, publish, distribute, sublicense, and/or
29
- *     sell copies of the Software, and to permit persons to whom the
30
- *     Software is furnished to do so, subject to the following
31
- *     conditions:
32
- *
33
- *     The above copyright notice and this permission notice shall be
34
- *     included in all copies or substantial portions of the Software.
35
- *
36
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43
- *     OTHER DEALINGS IN THE SOFTWARE.
444  */
455 
6
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
467 #include <dt-bindings/clock/meson8b-clkc.h>
478 #include <dt-bindings/gpio/meson8-gpio.h>
9
+#include <dt-bindings/power/meson8-power.h>
4810 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
4911 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
5012 #include "meson.dtsi"
....@@ -64,6 +26,8 @@
6426 			reg = <0x200>;
6527 			enable-method = "amlogic,meson8-smp";
6628 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
29
+			operating-points-v2 = <&cpu_opp_table>;
30
+			clocks = <&clkc CLKID_CPUCLK>;
6731 		};
6832 
6933 		cpu1: cpu@201 {
....@@ -73,6 +37,8 @@
7337 			reg = <0x201>;
7438 			enable-method = "amlogic,meson8-smp";
7539 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
40
+			operating-points-v2 = <&cpu_opp_table>;
41
+			clocks = <&clkc CLKID_CPUCLK>;
7642 		};
7743 
7844 		cpu2: cpu@202 {
....@@ -82,6 +48,8 @@
8248 			reg = <0x202>;
8349 			enable-method = "amlogic,meson8-smp";
8450 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
51
+			operating-points-v2 = <&cpu_opp_table>;
52
+			clocks = <&clkc CLKID_CPUCLK>;
8553 		};
8654 
8755 		cpu3: cpu@203 {
....@@ -91,6 +59,98 @@
9159 			reg = <0x203>;
9260 			enable-method = "amlogic,meson8-smp";
9361 			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
62
+			operating-points-v2 = <&cpu_opp_table>;
63
+			clocks = <&clkc CLKID_CPUCLK>;
64
+		};
65
+	};
66
+
67
+	cpu_opp_table: opp-table {
68
+		compatible = "operating-points-v2";
69
+		opp-shared;
70
+
71
+		opp-96000000 {
72
+			opp-hz = /bits/ 64 <96000000>;
73
+			opp-microvolt = <825000>;
74
+		};
75
+		opp-192000000 {
76
+			opp-hz = /bits/ 64 <192000000>;
77
+			opp-microvolt = <825000>;
78
+		};
79
+		opp-312000000 {
80
+			opp-hz = /bits/ 64 <312000000>;
81
+			opp-microvolt = <825000>;
82
+		};
83
+		opp-408000000 {
84
+			opp-hz = /bits/ 64 <408000000>;
85
+			opp-microvolt = <825000>;
86
+		};
87
+		opp-504000000 {
88
+			opp-hz = /bits/ 64 <504000000>;
89
+			opp-microvolt = <825000>;
90
+		};
91
+		opp-600000000 {
92
+			opp-hz = /bits/ 64 <600000000>;
93
+			opp-microvolt = <850000>;
94
+		};
95
+		opp-720000000 {
96
+			opp-hz = /bits/ 64 <720000000>;
97
+			opp-microvolt = <850000>;
98
+		};
99
+		opp-816000000 {
100
+			opp-hz = /bits/ 64 <816000000>;
101
+			opp-microvolt = <875000>;
102
+		};
103
+		opp-1008000000 {
104
+			opp-hz = /bits/ 64 <1008000000>;
105
+			opp-microvolt = <925000>;
106
+		};
107
+		opp-1200000000 {
108
+			opp-hz = /bits/ 64 <1200000000>;
109
+			opp-microvolt = <975000>;
110
+		};
111
+		opp-1416000000 {
112
+			opp-hz = /bits/ 64 <1416000000>;
113
+			opp-microvolt = <1025000>;
114
+		};
115
+		opp-1608000000 {
116
+			opp-hz = /bits/ 64 <1608000000>;
117
+			opp-microvolt = <1100000>;
118
+		};
119
+		opp-1800000000 {
120
+			status = "disabled";
121
+			opp-hz = /bits/ 64 <1800000000>;
122
+			opp-microvolt = <1125000>;
123
+		};
124
+		opp-1992000000 {
125
+			status = "disabled";
126
+			opp-hz = /bits/ 64 <1992000000>;
127
+			opp-microvolt = <1150000>;
128
+		};
129
+	};
130
+
131
+	gpu_opp_table: gpu-opp-table {
132
+		compatible = "operating-points-v2";
133
+
134
+		opp-182142857 {
135
+			opp-hz = /bits/ 64 <182142857>;
136
+			opp-microvolt = <1150000>;
137
+		};
138
+		opp-318750000 {
139
+			opp-hz = /bits/ 64 <318750000>;
140
+			opp-microvolt = <1150000>;
141
+		};
142
+		opp-425000000 {
143
+			opp-hz = /bits/ 64 <425000000>;
144
+			opp-microvolt = <1150000>;
145
+		};
146
+		opp-510000000 {
147
+			opp-hz = /bits/ 64 <510000000>;
148
+			opp-microvolt = <1150000>;
149
+		};
150
+		opp-637500000 {
151
+			opp-hz = /bits/ 64 <637500000>;
152
+			opp-microvolt = <1150000>;
153
+			turbo-mode;
94154 		};
95155 	};
96156 
....@@ -130,9 +190,76 @@
130190 		};
131191 	};
132192 
133
-	scu@c4300000 {
134
-		compatible = "arm,cortex-a9-scu";
135
-		reg = <0xc4300000 0x100>;
193
+	mmcbus: bus@c8000000 {
194
+		compatible = "simple-bus";
195
+		reg = <0xc8000000 0x8000>;
196
+		#address-cells = <1>;
197
+		#size-cells = <1>;
198
+		ranges = <0x0 0xc8000000 0x8000>;
199
+
200
+		ddr_clkc: clock-controller@400 {
201
+			compatible = "amlogic,meson8-ddr-clkc";
202
+			reg = <0x400 0x20>;
203
+			clocks = <&xtal>;
204
+			clock-names = "xtal";
205
+			#clock-cells = <1>;
206
+		};
207
+
208
+		dmcbus: bus@6000 {
209
+			compatible = "simple-bus";
210
+			reg = <0x6000 0x400>;
211
+			#address-cells = <1>;
212
+			#size-cells = <1>;
213
+			ranges = <0x0 0x6000 0x400>;
214
+
215
+			canvas: video-lut@20 {
216
+				compatible = "amlogic,meson8-canvas",
217
+					     "amlogic,canvas";
218
+				reg = <0x20 0x14>;
219
+			};
220
+		};
221
+	};
222
+
223
+	apb: bus@d0000000 {
224
+		compatible = "simple-bus";
225
+		reg = <0xd0000000 0x200000>;
226
+		#address-cells = <1>;
227
+		#size-cells = <1>;
228
+		ranges = <0x0 0xd0000000 0x200000>;
229
+
230
+		mali: gpu@c0000 {
231
+			compatible = "amlogic,meson8-mali", "arm,mali-450";
232
+			reg = <0xc0000 0x40000>;
233
+			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
234
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
235
+				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
236
+				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
237
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
238
+				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
239
+				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
240
+				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
241
+				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
242
+				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
243
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
244
+				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
245
+				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
246
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
247
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
248
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
249
+			interrupt-names = "gp", "gpmmu", "pp", "pmu",
250
+					  "pp0", "ppmmu0", "pp1", "ppmmu1",
251
+					  "pp2", "ppmmu2", "pp4", "ppmmu4",
252
+					  "pp5", "ppmmu5", "pp6", "ppmmu6";
253
+			resets = <&reset RESET_MALI>;
254
+
255
+			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
256
+			clock-names = "bus", "core";
257
+
258
+			assigned-clocks = <&clkc CLKID_MALI>;
259
+			assigned-clock-rates = <318750000>;
260
+
261
+			operating-points-v2 = <&gpu_opp_table>;
262
+		};
136263 	};
137264 }; /* end of / */
138265 
....@@ -163,6 +290,7 @@
163290 			mux {
164291 				groups = "uart_tx_ao_a", "uart_rx_ao_a";
165292 				function = "uart_ao";
293
+				bias-disable;
166294 			};
167295 		};
168296 
....@@ -170,6 +298,7 @@
170298 			mux {
171299 				groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
172300 				function = "i2c_mst_ao";
301
+				bias-disable;
173302 			};
174303 		};
175304 
....@@ -177,6 +306,7 @@
177306 			mux {
178307 				groups = "remote_input";
179308 				function = "remote";
309
+				bias-disable;
180310 			};
181311 		};
182312 
....@@ -184,19 +314,13 @@
184314 			mux {
185315 				groups = "pwm_f_ao";
186316 				function = "pwm_f_ao";
317
+				bias-disable;
187318 			};
188319 		};
189320 	};
190321 };
191322 
192323 &cbus {
193
-	clkc: clock-controller@4000 {
194
-		#clock-cells = <1>;
195
-		#reset-cells = <1>;
196
-		compatible = "amlogic,meson8-clkc";
197
-		reg = <0x8000 0x4>, <0x4000 0x400>;
198
-	};
199
-
200324 	reset: reset-controller@4404 {
201325 		compatible = "amlogic,meson8b-reset";
202326 		reg = <0x4404 0x9c>;
....@@ -213,6 +337,11 @@
213337 		reg = <0x86c0 0x10>;
214338 		#pwm-cells = <3>;
215339 		status = "disabled";
340
+	};
341
+
342
+	clock-measure@8758 {
343
+		compatible = "amlogic,meson8-clk-measure";
344
+		reg = <0x8758 0x1c>;
216345 	};
217346 
218347 	pinctrl_cbus: pinctrl@9880 {
....@@ -238,6 +367,7 @@
238367 				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
239368 					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
240369 				function = "sd_a";
370
+				bias-disable;
241371 			};
242372 		};
243373 
....@@ -246,6 +376,7 @@
246376 				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
247377 					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
248378 				function = "sd_b";
379
+				bias-disable;
249380 			};
250381 		};
251382 
....@@ -254,6 +385,16 @@
254385 				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
255386 					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
256387 				function = "sd_c";
388
+				bias-disable;
389
+			};
390
+		};
391
+
392
+		sdxc_b_pins: sdxc-b {
393
+			mux {
394
+				groups = "sdxc_d0_b", "sdxc_d13_b",
395
+					 "sdxc_clk_b", "sdxc_cmd_b";
396
+				function = "sdxc_b";
397
+				bias-pull-up;
257398 			};
258399 		};
259400 
....@@ -261,6 +402,7 @@
261402 			mux {
262403 				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
263404 				function = "nor";
405
+				bias-disable;
264406 			};
265407 		};
266408 
....@@ -272,6 +414,7 @@
272414 					 "eth_rxd1", "eth_rxd0", "eth_mdio",
273415 					 "eth_mdc";
274416 				function = "ethernet";
417
+				bias-disable;
275418 			};
276419 		};
277420 
....@@ -279,6 +422,7 @@
279422 			mux {
280423 				groups = "pwm_e";
281424 				function = "pwm_e";
425
+				bias-disable;
282426 			};
283427 		};
284428 
....@@ -287,6 +431,7 @@
287431 				groups = "uart_tx_a1",
288432 				       "uart_rx_a1";
289433 				function = "uart_a";
434
+				bias-disable;
290435 			};
291436 		};
292437 
....@@ -295,6 +440,7 @@
295440 				groups = "uart_cts_a1",
296441 				       "uart_rts_a1";
297442 				function = "uart_a";
443
+				bias-disable;
298444 			};
299445 		};
300446 	};
....@@ -311,16 +457,43 @@
311457 	compatible = "amlogic,meson8-efuse";
312458 	clocks = <&clkc CLKID_EFUSE>;
313459 	clock-names = "core";
460
+
461
+	temperature_calib: calib@1f4 {
462
+		/* only the upper two bytes are relevant */
463
+		reg = <0x1f4 0x4>;
464
+	};
314465 };
315466 
316467 &ethmac {
317468 	clocks = <&clkc CLKID_ETH>;
318469 	clock-names = "stmmaceth";
470
+
471
+	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
319472 };
320473 
321474 &gpio_intc {
322475 	compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
323476 	status = "okay";
477
+};
478
+
479
+&hhi {
480
+	clkc: clock-controller {
481
+		compatible = "amlogic,meson8-clkc";
482
+		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
483
+		clock-names = "xtal", "ddr_pll";
484
+		#clock-cells = <1>;
485
+		#reset-cells = <1>;
486
+	};
487
+
488
+	pwrc: power-controller {
489
+		compatible = "amlogic,meson8-pwrc";
490
+		#power-domain-cells = <1>;
491
+		amlogic,ao-sysctrl = <&pmu>;
492
+		clocks = <&clkc CLKID_VPU>;
493
+		clock-names = "vpu";
494
+		assigned-clocks = <&clkc CLKID_VPU>;
495
+		assigned-clock-rates = <364285714>;
496
+	};
324497 };
325498 
326499 &hwrng {
....@@ -350,6 +523,33 @@
350523 	arm,shared-override;
351524 };
352525 
526
+&periph {
527
+	scu@0 {
528
+		compatible = "arm,cortex-a9-scu";
529
+		reg = <0x0 0x100>;
530
+	};
531
+
532
+	timer@200 {
533
+		compatible = "arm,cortex-a9-global-timer";
534
+		reg = <0x200 0x20>;
535
+		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
536
+		clocks = <&clkc CLKID_PERIPH>;
537
+
538
+		/*
539
+		 * the arm_global_timer driver currently does not handle clock
540
+		 * rate changes. Keep it disabled for now.
541
+		 */
542
+		status = "disabled";
543
+	};
544
+
545
+	timer@600 {
546
+		compatible = "arm,cortex-a9-twd-timer";
547
+		reg = <0x600 0x20>;
548
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
549
+		clocks = <&clkc CLKID_PERIPH>;
550
+	};
551
+};
552
+
353553 &pwm_ab {
354554 	compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
355555 };
....@@ -358,11 +558,28 @@
358558 	compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
359559 };
360560 
561
+&rtc {
562
+	compatible = "amlogic,meson8-rtc";
563
+	resets = <&reset RESET_RTC>;
564
+};
565
+
361566 &saradc {
362567 	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
363
-	clocks = <&clkc CLKID_XTAL>,
364
-		<&clkc CLKID_SAR_ADC>;
568
+	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
365569 	clock-names = "clkin", "core";
570
+	amlogic,hhi-sysctrl = <&hhi>;
571
+	nvmem-cells = <&temperature_calib>;
572
+	nvmem-cell-names = "temperature_calib";
573
+};
574
+
575
+&sdhc {
576
+	compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
577
+	clocks = <&xtal>,
578
+		 <&clkc CLKID_FCLK_DIV4>,
579
+		 <&clkc CLKID_FCLK_DIV3>,
580
+		 <&clkc CLKID_FCLK_DIV5>,
581
+		 <&clkc CLKID_SDHC>;
582
+	clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
366583 };
367584 
368585 &sdio {
....@@ -375,28 +592,33 @@
375592 	clocks = <&clkc CLKID_CLK81>;
376593 };
377594 
595
+&timer_abcde {
596
+	clocks = <&xtal>, <&clkc CLKID_CLK81>;
597
+	clock-names = "xtal", "pclk";
598
+};
599
+
378600 &uart_AO {
379
-	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
380
-	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
381
-	clock-names = "baud", "xtal", "pclk";
601
+	compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
602
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
603
+	clock-names = "xtal", "pclk", "baud";
382604 };
383605 
384606 &uart_A {
385
-	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
386
-	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
387
-	clock-names = "baud", "xtal", "pclk";
607
+	compatible = "amlogic,meson8-uart";
608
+	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
609
+	clock-names = "xtal", "pclk", "baud";
388610 };
389611 
390612 &uart_B {
391
-	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
392
-	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
393
-	clock-names = "baud", "xtal", "pclk";
613
+	compatible = "amlogic,meson8-uart";
614
+	clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
615
+	clock-names = "xtal", "pclk", "baud";
394616 };
395617 
396618 &uart_C {
397
-	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
398
-	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
399
-	clock-names = "baud", "xtal", "pclk";
619
+	compatible = "amlogic,meson8-uart";
620
+	clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
621
+	clock-names = "xtal", "pclk", "baud";
400622 };
401623 
402624 &usb0 {