disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/imx6sl.dtsi
..
..
@@ -23,6 +23,13 @@
23
23
 		gpio2 = &gpio3;
24
24
 		gpio3 = &gpio4;
25
25
 		gpio4 = &gpio5;
26
+		i2c0 = &i2c1;
27
+		i2c1 = &i2c2;
28
+		i2c2 = &i2c3;
29
+		mmc0 = &usdhc1;
30
+		mmc1 = &usdhc2;
31
+		mmc2 = &usdhc3;
32
+		mmc3 = &usdhc4;
26
33
 		serial0 = &uart1;
27
34
 		serial1 = &uart2;
28
35
 		serial2 = &uart3;
..
..
@@ -32,6 +39,9 @@
32
39
 		spi1 = &ecspi2;
33
40
 		spi2 = &ecspi3;
34
41
 		spi3 = &ecspi4;
42
+		usb0 = &usbotg1;
43
+		usb1 = &usbotg2;
44
+		usb2 = &usbh;
35
45
 		usbphy0 = &usbphy1;
36
46
 		usbphy1 = &usbphy2;
37
47
 	};
..
..
@@ -67,16 +77,9 @@
67
77
 			arm-supply = <&reg_arm>;
68
78
 			pu-supply = <&reg_pu>;
69
79
 			soc-supply = <&reg_soc>;
80
+			nvmem-cells = <&cpu_speed_grade>;
81
+			nvmem-cell-names = "speed_grade";
70
82
 		};
71
-	};
72
-
73
-	intc: interrupt-controller@a01000 {
74
-		compatible = "arm,cortex-a9-gic";
75
-		#interrupt-cells = <3>;
76
-		interrupt-controller;
77
-		reg = <0x00a01000 0x1000>,
78
-		      <0x00a00100 0x100>;
79
-		interrupt-parent = <&intc>;
80
83
 	};
81
84
 
82
85
 	clocks {
..
..
@@ -93,19 +96,15 @@
93
96
 		};
94
97
 	};
95
98
 
96
-	tempmon: tempmon {
97
-		compatible = "fsl,imx6q-tempmon";
98
-		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
99
-		interrupt-parent = <&gpc>;
100
-		fsl,tempmon = <&anatop>;
101
-		fsl,tempmon-data = <&ocotp>;
102
-		clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
103
-	};
104
-
105
99
 	pmu {
106
100
 		compatible = "arm,cortex-a9-pmu";
107
101
 		interrupt-parent = <&gpc>;
108
102
 		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
103
+	};
104
+
105
+	usbphynop1: usbphynop1 {
106
+		compatible = "usb-nop-xceiv";
107
+		#phy-cells = <0>;
109
108
 	};
110
109
 
111
110
 	soc {
..
..
@@ -118,10 +117,22 @@
118
117
 		ocram: sram@900000 {
119
118
 			compatible = "mmio-sram";
120
119
 			reg = <0x00900000 0x20000>;
120
+			ranges = <0 0x00900000 0x20000>;
121
+			#address-cells = <1>;
122
+			#size-cells = <1>;
121
123
 			clocks = <&clks IMX6SL_CLK_OCRAM>;
122
124
 		};
123
125
 
124
-		L2: l2-cache@a02000 {
126
+		intc: interrupt-controller@a01000 {
127
+			compatible = "arm,cortex-a9-gic";
128
+			#interrupt-cells = <3>;
129
+			interrupt-controller;
130
+			reg = <0x00a01000 0x1000>,
131
+			      <0x00a00100 0x100>;
132
+			interrupt-parent = <&intc>;
133
+		};
134
+
135
+		L2: cache-controller@a02000 {
125
136
 			compatible = "arm,pl310-cache";
126
137
 			reg = <0x00a02000 0x1000>;
127
138
 			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -131,7 +142,7 @@
131
142
 			arm,data-latency = <4 2 3>;
132
143
 		};
133
144
 
134
-		aips1: aips-bus@2000000 {
145
+		aips1: bus@2000000 {
135
146
 			compatible = "fsl,aips-bus", "simple-bus";
136
147
 			#address-cells = <1>;
137
148
 			#size-cells = <1>;
..
..
@@ -166,7 +177,7 @@
166
177
 					status = "disabled";
167
178
 				};
168
179
 
169
-				ecspi1: ecspi@2008000 {
180
+				ecspi1: spi@2008000 {
170
181
 					#address-cells = <1>;
171
182
 					#size-cells = <0>;
172
183
 					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
..
..
@@ -178,7 +189,7 @@
178
189
 					status = "disabled";
179
190
 				};
180
191
 
181
-				ecspi2: ecspi@200c000 {
192
+				ecspi2: spi@200c000 {
182
193
 					#address-cells = <1>;
183
194
 					#size-cells = <0>;
184
195
 					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
..
..
@@ -190,7 +201,7 @@
190
201
 					status = "disabled";
191
202
 				};
192
203
 
193
-				ecspi3: ecspi@2010000 {
204
+				ecspi3: spi@2010000 {
194
205
 					#address-cells = <1>;
195
206
 					#size-cells = <0>;
196
207
 					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
..
..
@@ -202,7 +213,7 @@
202
213
 					status = "disabled";
203
214
 				};
204
215
 
205
-				ecspi4: ecspi@2014000 {
216
+				ecspi4: spi@2014000 {
206
217
 					#address-cells = <1>;
207
218
 					#size-cells = <0>;
208
219
 					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
..
..
@@ -329,46 +340,46 @@
329
340
 			};
330
341
 
331
342
 			pwm1: pwm@2080000 {
332
-				#pwm-cells = <2>;
343
+				#pwm-cells = <3>;
333
344
 				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
334
345
 				reg = <0x02080000 0x4000>;
335
346
 				interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
336
-				clocks = <&clks IMX6SL_CLK_PWM1>,
347
+				clocks = <&clks IMX6SL_CLK_PERCLK>,
337
348
 					 <&clks IMX6SL_CLK_PWM1>;
338
349
 				clock-names = "ipg", "per";
339
350
 			};
340
351
 
341
352
 			pwm2: pwm@2084000 {
342
-				#pwm-cells = <2>;
353
+				#pwm-cells = <3>;
343
354
 				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
344
355
 				reg = <0x02084000 0x4000>;
345
356
 				interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
346
-				clocks = <&clks IMX6SL_CLK_PWM2>,
357
+				clocks = <&clks IMX6SL_CLK_PERCLK>,
347
358
 					 <&clks IMX6SL_CLK_PWM2>;
348
359
 				clock-names = "ipg", "per";
349
360
 			};
350
361
 
351
362
 			pwm3: pwm@2088000 {
352
-				#pwm-cells = <2>;
363
+				#pwm-cells = <3>;
353
364
 				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
354
365
 				reg = <0x02088000 0x4000>;
355
366
 				interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
356
-				clocks = <&clks IMX6SL_CLK_PWM3>,
367
+				clocks = <&clks IMX6SL_CLK_PERCLK>,
357
368
 					 <&clks IMX6SL_CLK_PWM3>;
358
369
 				clock-names = "ipg", "per";
359
370
 			};
360
371
 
361
372
 			pwm4: pwm@208c000 {
362
-				#pwm-cells = <2>;
373
+				#pwm-cells = <3>;
363
374
 				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
364
375
 				reg = <0x0208c000 0x4000>;
365
376
 				interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
366
-				clocks = <&clks IMX6SL_CLK_PWM4>,
377
+				clocks = <&clks IMX6SL_CLK_PERCLK>,
367
378
 					 <&clks IMX6SL_CLK_PWM4>;
368
379
 				clock-names = "ipg", "per";
369
380
 			};
370
381
 
371
-			gpt: gpt@2098000 {
382
+			gpt: timer@2098000 {
372
383
 				compatible = "fsl,imx6sl-gpt";
373
384
 				reg = <0x02098000 0x4000>;
374
385
 				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -479,30 +490,30 @@
479
490
 					      <&iomuxc 21 161 1>;
480
491
 			};
481
492
 
482
-			kpp: kpp@20b8000 {
493
+			kpp: keypad@20b8000 {
483
494
 				compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
484
495
 				reg = <0x020b8000 0x4000>;
485
496
 				interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
486
-				clocks = <&clks IMX6SL_CLK_DUMMY>;
497
+				clocks = <&clks IMX6SL_CLK_IPG>;
487
498
 				status = "disabled";
488
499
 			};
489
500
 
490
-			wdog1: wdog@20bc000 {
501
+			wdog1: watchdog@20bc000 {
491
502
 				compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
492
503
 				reg = <0x020bc000 0x4000>;
493
504
 				interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
494
-				clocks = <&clks IMX6SL_CLK_DUMMY>;
505
+				clocks = <&clks IMX6SL_CLK_IPG>;
495
506
 			};
496
507
 
497
-			wdog2: wdog@20c0000 {
508
+			wdog2: watchdog@20c0000 {
498
509
 				compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
499
510
 				reg = <0x020c0000 0x4000>;
500
511
 				interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
501
-				clocks = <&clks IMX6SL_CLK_DUMMY>;
512
+				clocks = <&clks IMX6SL_CLK_IPG>;
502
513
 				status = "disabled";
503
514
 			};
504
515
 
505
-			clks: ccm@20c4000 {
516
+			clks: clock-controller@20c4000 {
506
517
 				compatible = "fsl,imx6sl-ccm";
507
518
 				reg = <0x020c4000 0x4000>;
508
519
 				interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
..
..
@@ -513,13 +524,13 @@
513
524
 			anatop: anatop@20c8000 {
514
525
 				compatible = "fsl,imx6sl-anatop",
515
526
 					     "fsl,imx6q-anatop",
516
-					     "syscon", "simple-bus";
527
+					     "syscon", "simple-mfd";
517
528
 				reg = <0x020c8000 0x1000>;
518
529
 				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
519
530
 					     <0 54 IRQ_TYPE_LEVEL_HIGH>,
520
531
 					     <0 127 IRQ_TYPE_LEVEL_HIGH>;
521
532
 
522
-				regulator-1p1 {
533
+				reg_vdd1p1: regulator-1p1 {
523
534
 					compatible = "fsl,anatop-regulator";
524
535
 					regulator-name = "vdd1p1";
525
536
 					regulator-min-microvolt = <1000000>;
..
..
@@ -534,7 +545,7 @@
534
545
 					anatop-enable-bit = <0>;
535
546
 				};
536
547
 
537
-				regulator-3p0 {
548
+				reg_vdd3p0: regulator-3p0 {
538
549
 					compatible = "fsl,anatop-regulator";
539
550
 					regulator-name = "vdd3p0";
540
551
 					regulator-min-microvolt = <2800000>;
..
..
@@ -549,7 +560,7 @@
549
560
 					anatop-enable-bit = <0>;
550
561
 				};
551
562
 
552
-				regulator-2p5 {
563
+				reg_vdd2p5: regulator-2p5 {
553
564
 					compatible = "fsl,anatop-regulator";
554
565
 					regulator-name = "vdd2p5";
555
566
 					regulator-min-microvolt = <2250000>;
..
..
@@ -586,7 +597,6 @@
586
597
 					regulator-name = "vddpu";
587
598
 					regulator-min-microvolt = <725000>;
588
599
 					regulator-max-microvolt = <1450000>;
589
-					regulator-always-on;
590
600
 					anatop-reg-offset = <0x140>;
591
601
 					anatop-vol-bit-shift = <9>;
592
602
 					anatop-vol-bit-width = <5>;
..
..
@@ -613,6 +623,16 @@
613
623
 					anatop-min-bit-val = <1>;
614
624
 					anatop-min-voltage = <725000>;
615
625
 					anatop-max-voltage = <1450000>;
626
+				};
627
+
628
+				tempmon: tempmon {
629
+					compatible = "fsl,imx6q-tempmon";
630
+					interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
631
+					interrupt-parent = <&gpc>;
632
+					fsl,tempmon = <&anatop>;
633
+					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
634
+					nvmem-cell-names = "calib", "temp_grade";
635
+					clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
616
636
 				};
617
637
 			};
618
638
 
..
..
@@ -664,7 +684,7 @@
664
684
 				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
665
685
 			};
666
686
 
667
-			src: src@20d8000 {
687
+			src: reset-controller@20d8000 {
668
688
 				compatible = "fsl,imx6sl-src", "fsl,imx51-src";
669
689
 				reg = <0x020d8000 0x4000>;
670
690
 				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
..
..
@@ -717,7 +737,7 @@
717
737
 				reg = <0x020e0000 0x38>;
718
738
 			};
719
739
 
720
-			iomuxc: iomuxc@20e0000 {
740
+			iomuxc: pinctrl@20e0000 {
721
741
 				compatible = "fsl,imx6sl-iomuxc";
722
742
 				reg = <0x020e0000 0x4000>;
723
743
 			};
..
..
@@ -732,7 +752,7 @@
732
752
 				interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
733
753
 			};
734
754
 
735
-			sdma: sdma@20ec000 {
755
+			sdma: dma-controller@20ec000 {
736
756
 				compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
737
757
 				reg = <0x020ec000 0x4000>;
738
758
 				interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -766,7 +786,7 @@
766
786
 				power-domains = <&pd_disp>;
767
787
 			};
768
788
 
769
-			dcp: dcp@20fc000 {
789
+			dcp: crypto@20fc000 {
770
790
 				compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
771
791
 				reg = <0x020fc000 0x4000>;
772
792
 				interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
..
..
@@ -775,7 +795,7 @@
775
795
 			};
776
796
 		};
777
797
 
778
-		aips2: aips-bus@2100000 {
798
+		aips2: bus@2100000 {
779
799
 			compatible = "fsl,aips-bus", "simple-bus";
780
800
 			#address-cells = <1>;
781
801
 			#size-cells = <1>;
..
..
@@ -813,6 +833,8 @@
813
833
 				reg = <0x02184400 0x200>;
814
834
 				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
815
835
 				clocks = <&clks IMX6SL_CLK_USBOH3>;
836
+				fsl,usbphy = <&usbphynop1>;
837
+				phy_type = "hsic";
816
838
 				fsl,usbmisc = <&usbmisc 2>;
817
839
 				dr_mode = "host";
818
840
 				ahb-burst-config = <0x0>;
..
..
@@ -838,7 +860,7 @@
838
860
 				status = "disabled";
839
861
 			};
840
862
 
841
-			usdhc1: usdhc@2190000 {
863
+			usdhc1: mmc@2190000 {
842
864
 				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
843
865
 				reg = <0x02190000 0x4000>;
844
866
 				interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -850,7 +872,7 @@
850
872
 				status = "disabled";
851
873
 			};
852
874
 
853
-			usdhc2: usdhc@2194000 {
875
+			usdhc2: mmc@2194000 {
854
876
 				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
855
877
 				reg = <0x02194000 0x4000>;
856
878
 				interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -862,7 +884,7 @@
862
884
 				status = "disabled";
863
885
 			};
864
886
 
865
-			usdhc3: usdhc@2198000 {
887
+			usdhc3: mmc@2198000 {
866
888
 				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
867
889
 				reg = <0x02198000 0x4000>;
868
890
 				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -874,7 +896,7 @@
874
896
 				status = "disabled";
875
897
 			};
876
898
 
877
-			usdhc4: usdhc@219c000 {
899
+			usdhc4: mmc@219c000 {
878
900
 				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
879
901
 				reg = <0x0219c000 0x4000>;
880
902
 				interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -916,9 +938,10 @@
916
938
 				status = "disabled";
917
939
 			};
918
940
 
919
-			mmdc: mmdc@21b0000 {
941
+			memory-controller@21b0000 {
920
942
 				compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
921
943
 				reg = <0x021b0000 0x4000>;
944
+				clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
922
945
 			};
923
946
 
924
947
 			rngb: rngb@21b4000 {
..
..
@@ -937,10 +960,24 @@
937
960
 				status = "disabled";
938
961
 			};
939
962
 
940
-			ocotp: ocotp@21bc000 {
963
+			ocotp: efuse@21bc000 {
941
964
 				compatible = "fsl,imx6sl-ocotp", "syscon";
942
965
 				reg = <0x021bc000 0x4000>;
943
966
 				clocks = <&clks IMX6SL_CLK_OCOTP>;
967
+				#address-cells = <1>;
968
+				#size-cells = <1>;
969
+
970
+				cpu_speed_grade: speed-grade@10 {
971
+					reg = <0x10 4>;
972
+				};
973
+
974
+				tempmon_calib: calib@38 {
975
+					reg = <0x38 4>;
976
+				};
977
+
978
+				tempmon_temp_grade: temp-grade@20 {
979
+					reg = <0x20 4>;
980
+				};
944
981
 			};
945
982
 
946
983
 			audmux: audmux@21d8000 {