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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH |
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| 3 | | - * |
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| 4 | | - * The code contained herein is licensed under the GNU General Public |
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| 5 | | - * License. You may obtain a copy of the GNU General Public License |
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| 6 | | - * Version 2 or later at the following locations: |
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| 7 | | - * |
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| 8 | | - * http://www.opensource.org/licenses/gpl-license.html |
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| 9 | | - * http://www.gnu.org/copyleft/gpl.html |
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| 10 | 4 | */ |
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| 11 | 5 | |
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| 12 | 6 | #include <dt-bindings/gpio/gpio.h> |
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| .. | .. |
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| 16 | 10 | compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; |
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| 17 | 11 | |
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| 18 | 12 | memory@10000000 { |
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| 13 | + device_type = "memory"; |
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| 19 | 14 | reg = <0x10000000 0x80000000>; |
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| 20 | 15 | }; |
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| 21 | 16 | |
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| .. | .. |
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| 76 | 71 | pinctrl-names = "default"; |
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| 77 | 72 | pinctrl-0 = <&pinctrl_ecspi3>; |
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| 78 | 73 | status = "okay"; |
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| 79 | | - cs-gpios = <&gpio4 24 0>; |
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| 74 | + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; |
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| 80 | 75 | |
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| 81 | | - flash@0 { |
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| 76 | + som_flash: flash@0 { |
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| 82 | 77 | compatible = "m25p80", "jedec,spi-nor"; |
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| 83 | 78 | spi-max-frequency = <20000000>; |
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| 84 | 79 | reg = <0>; |
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| .. | .. |
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| 88 | 83 | &fec { |
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| 89 | 84 | pinctrl-names = "default"; |
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| 90 | 85 | pinctrl-0 = <&pinctrl_enet>; |
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| 86 | + phy-handle = <ðphy>; |
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| 91 | 87 | phy-mode = "rgmii"; |
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| 92 | 88 | phy-reset-duration = <10>; /* in msecs */ |
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| 93 | 89 | phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; |
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| 94 | 90 | phy-supply = <&vdd_eth_io_reg>; |
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| 95 | 91 | status = "disabled"; |
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| 92 | + |
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| 93 | + fec_mdio: mdio { |
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| 94 | + #address-cells = <1>; |
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| 95 | + #size-cells = <0>; |
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| 96 | + |
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| 97 | + ethphy: ethernet-phy@0 { |
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| 98 | + compatible = "ethernet-phy-ieee802.3-c22"; |
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| 99 | + reg = <0>; |
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| 100 | + txc-skew-ps = <1680>; |
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| 101 | + rxc-skew-ps = <1860>; |
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| 102 | + }; |
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| 103 | + }; |
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| 96 | 104 | }; |
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| 97 | 105 | |
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| 98 | 106 | &gpmi { |
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| .. | .. |
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| 107 | 115 | pinctrl-0 = <&pinctrl_i2c1>; |
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| 108 | 116 | status = "okay"; |
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| 109 | 117 | |
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| 110 | | - eeprom@50 { |
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| 118 | + som_eeprom: eeprom@50 { |
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| 111 | 119 | compatible = "atmel,24c32"; |
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| 112 | 120 | reg = <0x50>; |
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| 113 | 121 | }; |
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| .. | .. |
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| 117 | 125 | reg = <0x58>; |
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| 118 | 126 | interrupt-parent = <&gpio2>; |
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| 119 | 127 | interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ |
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| 128 | + interrupt-controller; |
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| 120 | 129 | |
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| 121 | 130 | regulators { |
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| 122 | 131 | vddcore_reg: bcore1 { |
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