disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/imx6q.dtsi
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@@ -49,6 +49,8 @@
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 			arm-supply = <&reg_arm>;
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 			pu-supply = <&reg_pu>;
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 			soc-supply = <&reg_soc>;
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+			nvmem-cells = <&cpu_speed_grade>;
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+			nvmem-cell-names = "speed_grade";
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 		};
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 		cpu1: cpu@1 {
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@@ -73,6 +75,7 @@
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 				396000	1175000
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 			>;
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 			clock-latency = <61036>; /* two CLK32 periods */
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+			#cooling-cells = <2>;
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 			clocks = <&clks IMX6QDL_CLK_ARM>,
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 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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 				 <&clks IMX6QDL_CLK_STEP>,
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@@ -107,6 +110,7 @@
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 				396000	1175000
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 			>;
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 			clock-latency = <61036>; /* two CLK32 periods */
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+			#cooling-cells = <2>;
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 			clocks = <&clks IMX6QDL_CLK_ARM>,
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 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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 				 <&clks IMX6QDL_CLK_STEP>,
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@@ -141,6 +145,7 @@
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 				396000	1175000
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 			>;
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 			clock-latency = <61036>; /* two CLK32 periods */
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+			#cooling-cells = <2>;
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 			clocks = <&clks IMX6QDL_CLK_ARM>,
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 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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 				 <&clks IMX6QDL_CLK_STEP>,
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@@ -158,12 +163,15 @@
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 		ocram: sram@900000 {
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 			compatible = "mmio-sram";
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 			reg = <0x00900000 0x40000>;
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+			ranges = <0 0x00900000 0x40000>;
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
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 		};
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-		aips-bus@2000000 { /* AIPS1 */
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+		bus@2000000 { /* AIPS1 */
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 			spba-bus@2000000 {
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-				ecspi5: ecspi@2018000 {
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+				ecspi5: spi@2018000 {
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 					#address-cells = <1>;
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 					#size-cells = <0>;
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 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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@@ -176,10 +184,6 @@
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 					dma-names = "rx", "tx";
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 					status = "disabled";
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 				};
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-			};
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-
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-			iomuxc: iomuxc@20e0000 {
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-				compatible = "fsl,imx6q-iomuxc";
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 			};
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 		};
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@@ -202,6 +206,7 @@
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 				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
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 			clock-names = "bus", "core";
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 			power-domains = <&pd_pu>;
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+			#cooling-cells = <2>;
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 		};
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 		ipu2: ipu@2800000 {
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@@ -421,6 +426,10 @@
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 	};
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 };
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+&iomuxc {
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+	compatible = "fsl,imx6q-iomuxc";
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+};
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+
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 &ipu1_csi1 {
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 	ipu1_csi1_from_mipi_vc1: endpoint {
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 		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;