| .. | .. |
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| 25 | 25 | usbdrdphy1 = &usbdrd_phy1; |
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| 26 | 26 | }; |
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| 27 | 27 | |
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| 28 | + arm_a7_pmu: arm-a7-pmu { |
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| 29 | + compatible = "arm,cortex-a7-pmu"; |
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| 30 | + interrupt-parent = <&gic>; |
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| 31 | + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |
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| 32 | + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, |
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| 33 | + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, |
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| 34 | + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
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| 35 | + status = "disabled"; |
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| 36 | + }; |
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| 37 | + |
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| 38 | + arm_a15_pmu: arm-a15-pmu { |
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| 39 | + compatible = "arm,cortex-a15-pmu"; |
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| 40 | + interrupt-parent = <&combiner>; |
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| 41 | + interrupts = <1 2>, |
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| 42 | + <7 0>, |
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| 43 | + <16 6>, |
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| 44 | + <19 2>; |
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| 45 | + status = "disabled"; |
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| 46 | + }; |
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| 47 | + |
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| 48 | + timer: timer { |
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| 49 | + compatible = "arm,armv7-timer"; |
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| 50 | + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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| 51 | + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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| 52 | + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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| 53 | + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
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| 54 | + clock-frequency = <24000000>; |
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| 55 | + }; |
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| 56 | + |
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| 28 | 57 | soc: soc { |
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| 29 | | - arm_a7_pmu: arm-a7-pmu { |
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| 30 | | - compatible = "arm,cortex-a7-pmu"; |
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| 31 | | - interrupt-parent = <&gic>; |
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| 32 | | - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |
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| 33 | | - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, |
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| 34 | | - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, |
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| 35 | | - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
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| 36 | | - status = "disabled"; |
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| 37 | | - }; |
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| 38 | | - |
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| 39 | | - arm_a15_pmu: arm-a15-pmu { |
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| 40 | | - compatible = "arm,cortex-a15-pmu"; |
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| 41 | | - interrupt-parent = <&combiner>; |
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| 42 | | - interrupts = <1 2>, |
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| 43 | | - <7 0>, |
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| 44 | | - <16 6>, |
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| 45 | | - <19 2>; |
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| 46 | | - status = "disabled"; |
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| 47 | | - }; |
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| 48 | | - |
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| 49 | | - sysram@2020000 { |
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| 58 | + sram@2020000 { |
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| 50 | 59 | compatible = "mmio-sram"; |
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| 51 | 60 | reg = <0x02020000 0x54000>; |
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| 52 | 61 | #address-cells = <1>; |
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| 53 | 62 | #size-cells = <1>; |
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| 54 | 63 | ranges = <0 0x02020000 0x54000>; |
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| 55 | 64 | |
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| 56 | | - smp-sysram@0 { |
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| 65 | + smp-sram@0 { |
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| 57 | 66 | compatible = "samsung,exynos4210-sysram"; |
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| 58 | 67 | reg = <0x0 0x1000>; |
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| 59 | 68 | }; |
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| 60 | 69 | |
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| 61 | | - smp-sysram@53000 { |
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| 70 | + smp-sram@53000 { |
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| 62 | 71 | compatible = "samsung,exynos4210-sysram-ns"; |
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| 63 | 72 | reg = <0x53000 0x1000>; |
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| 64 | 73 | }; |
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| 65 | 74 | }; |
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| 66 | 75 | |
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| 67 | | - mct: mct@101c0000 { |
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| 76 | + mct: timer@101c0000 { |
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| 68 | 77 | compatible = "samsung,exynos4210-mct"; |
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| 69 | 78 | reg = <0x101c0000 0xb00>; |
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| 70 | | - interrupt-parent = <&mct_map>; |
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| 71 | | - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, |
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| 72 | | - <8>, <9>, <10>, <11>; |
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| 73 | | - |
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| 74 | | - mct_map: mct-map { |
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| 75 | | - #interrupt-cells = <1>; |
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| 76 | | - #address-cells = <0>; |
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| 77 | | - #size-cells = <0>; |
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| 78 | | - interrupt-map = <0 &combiner 23 3>, |
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| 79 | | - <1 &combiner 23 4>, |
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| 80 | | - <2 &combiner 25 2>, |
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| 81 | | - <3 &combiner 25 3>, |
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| 82 | | - <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, |
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| 83 | | - <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>, |
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| 84 | | - <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>, |
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| 85 | | - <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>, |
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| 86 | | - <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>, |
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| 87 | | - <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>, |
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| 88 | | - <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>, |
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| 89 | | - <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; |
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| 90 | | - }; |
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| 79 | + interrupts-extended = <&combiner 23 3>, |
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| 80 | + <&combiner 23 4>, |
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| 81 | + <&combiner 25 2>, |
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| 82 | + <&combiner 25 3>, |
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| 83 | + <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
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| 84 | + <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
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| 85 | + <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
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| 86 | + <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
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| 87 | + <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
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| 88 | + <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
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| 89 | + <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
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| 90 | + <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
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| 91 | 91 | }; |
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| 92 | 92 | |
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| 93 | 93 | watchdog: watchdog@101d0000 { |
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| 94 | 94 | compatible = "samsung,exynos5420-wdt"; |
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| 95 | 95 | reg = <0x101d0000 0x100>; |
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| 96 | 96 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
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| 97 | + }; |
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| 98 | + |
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| 99 | + adc: adc@12d10000 { |
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| 100 | + compatible = "samsung,exynos-adc-v2"; |
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| 101 | + reg = <0x12d10000 0x100>; |
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| 102 | + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
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| 103 | + #io-channel-cells = <1>; |
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| 104 | + io-channel-ranges; |
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| 105 | + status = "disabled"; |
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| 97 | 106 | }; |
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| 98 | 107 | |
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| 99 | 108 | /* i2c_0-3 are defined in exynos5.dtsi */ |
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| .. | .. |
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| 180 | 189 | compatible = "samsung,exynos4210-ehci"; |
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| 181 | 190 | reg = <0x12110000 0x100>; |
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| 182 | 191 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
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| 183 | | - |
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| 184 | | - #address-cells = <1>; |
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| 185 | | - #size-cells = <0>; |
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| 186 | | - port@0 { |
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| 187 | | - reg = <0>; |
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| 188 | | - phys = <&usb2_phy 1>; |
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| 189 | | - }; |
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| 192 | + phys = <&usb2_phy 1>; |
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| 193 | + phy-names = "host"; |
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| 190 | 194 | }; |
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| 191 | 195 | |
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| 192 | 196 | usbhost1: usb@12120000 { |
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| 193 | 197 | compatible = "samsung,exynos4210-ohci"; |
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| 194 | 198 | reg = <0x12120000 0x100>; |
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| 195 | 199 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
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| 196 | | - |
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| 197 | | - #address-cells = <1>; |
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| 198 | | - #size-cells = <0>; |
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| 199 | | - port@0 { |
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| 200 | | - reg = <0>; |
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| 201 | | - phys = <&usb2_phy 1>; |
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| 202 | | - }; |
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| 200 | + phys = <&usb2_phy 1>; |
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| 201 | + phy-names = "host"; |
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| 203 | 202 | }; |
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| 204 | 203 | |
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| 205 | 204 | usb2_phy: phy@12130000 { |
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