disable i2c1

hc

2024-05-11 645e752c5a84baeb21015cdc85fc05b7d16312c8

 kernel/arch/arm/boot/dts/dra76-evm.dts
..
..
@@ -1,9 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
3
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
7
4
  */
8
5
 /dts-v1/;
9
6
 
..
..
@@ -16,9 +13,50 @@
16
13
 	model = "TI DRA762 EVM";
17
14
 	compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
18
15
 
16
+	aliases {
17
+		display0 = &hdmi0;
18
+
19
+		sound0 = &sound0;
20
+		sound1 = &hdmi;
21
+	};
22
+
19
23
 	memory@0 {
20
24
 		device_type = "memory";
21
25
 		reg = <0x0 0x80000000 0x0 0x80000000>;
26
+	};
27
+
28
+	reserved-memory {
29
+		#address-cells = <2>;
30
+		#size-cells = <2>;
31
+		ranges;
32
+
33
+		ipu2_cma_pool: ipu2_cma@95800000 {
34
+			compatible = "shared-dma-pool";
35
+			reg = <0x0 0x95800000 0x0 0x3800000>;
36
+			reusable;
37
+			status = "okay";
38
+		};
39
+
40
+		dsp1_cma_pool: dsp1_cma@99000000 {
41
+			compatible = "shared-dma-pool";
42
+			reg = <0x0 0x99000000 0x0 0x4000000>;
43
+			reusable;
44
+			status = "okay";
45
+		};
46
+
47
+		ipu1_cma_pool: ipu1_cma@9d000000 {
48
+			compatible = "shared-dma-pool";
49
+			reg = <0x0 0x9d000000 0x0 0x2000000>;
50
+			reusable;
51
+			status = "okay";
52
+		};
53
+
54
+		dsp2_cma_pool: dsp2_cma@9f000000 {
55
+			compatible = "shared-dma-pool";
56
+			reg = <0x0 0x9f000000 0x0 0x800000>;
57
+			reusable;
58
+			status = "okay";
59
+		};
22
60
 	};
23
61
 
24
62
 	vsys_12v0: fixedregulator-vsys12v0 {
..
..
@@ -118,6 +156,54 @@
118
156
 		vin-supply = <&vio_3v3>;
119
157
 		regulator-min-microvolt = <1800000>;
120
158
 		regulator-max-microvolt = <1800000>;
159
+	};
160
+
161
+	clk_ov5640_fixed: clock {
162
+		compatible = "fixed-clock";
163
+		#clock-cells = <0>;
164
+		clock-frequency = <24000000>;
165
+	};
166
+
167
+	hdmi0: connector {
168
+		compatible = "hdmi-connector";
169
+		label = "hdmi";
170
+
171
+		type = "a";
172
+
173
+		port {
174
+			hdmi_connector_in: endpoint {
175
+				remote-endpoint = <&tpd12s015_out>;
176
+			};
177
+		};
178
+	};
179
+
180
+	tpd12s015: encoder {
181
+		compatible = "ti,tpd12s015";
182
+
183
+		gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>,   /* gpio7_30, CT CP HPD */
184
+			<&gpio7 31 GPIO_ACTIVE_HIGH>,   /* gpio7_31, LS OE */
185
+			<&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
186
+
187
+		ports {
188
+			#address-cells = <1>;
189
+			#size-cells = <0>;
190
+
191
+			port@0 {
192
+				reg = <0>;
193
+
194
+				tpd12s015_in: endpoint {
195
+					remote-endpoint = <&hdmi_out>;
196
+				};
197
+			};
198
+
199
+			port@1 {
200
+				reg = <1>;
201
+
202
+				tpd12s015_out: endpoint {
203
+					remote-endpoint = <&hdmi_connector_in>;
204
+				};
205
+			};
206
+		};
121
207
 	};
122
208
 };
123
209
 
..
..
@@ -320,6 +406,27 @@
320
406
 	};
321
407
 };
322
408
 
409
+&i2c5 {
410
+	status = "okay";
411
+	clock-frequency = <400000>;
412
+
413
+	ov5640@3c {
414
+		compatible = "ovti,ov5640";
415
+		reg = <0x3c>;
416
+
417
+		clocks = <&clk_ov5640_fixed>;
418
+		clock-names = "xclk";
419
+
420
+		port {
421
+			csi2_cam0: endpoint {
422
+				remote-endpoint = <&csi2_phy0>;
423
+				clock-lanes = <0>;
424
+				data-lanes = <1 2>;
425
+			};
426
+		};
427
+	};
428
+};
429
+
323
430
 &cpu0 {
324
431
 	vdd-supply = <&buck10_reg>;
325
432
 };
..
..
@@ -368,25 +475,23 @@
368
475
 	status = "disabled";
369
476
 };
370
477
 
371
-&mac {
478
+&mac_sw {
372
479
 	status = "okay";
373
-
374
-	dual_emac;
375
480
 };
376
481
 
377
-&cpsw_emac0 {
378
-	phy_id = <&davinci_mdio>, <2>;
482
+&cpsw_port1 {
483
+	phy-handle = <&dp83867_0>;
379
484
 	phy-mode = "rgmii-id";
380
-	dual_emac_res_vlan = <1>;
485
+	ti,dual-emac-pvid = <1>;
381
486
 };
382
487
 
383
-&cpsw_emac1 {
384
-	phy_id = <&davinci_mdio>, <3>;
488
+&cpsw_port2 {
489
+	phy-handle = <&dp83867_1>;
385
490
 	phy-mode = "rgmii-id";
386
-	dual_emac_res_vlan = <2>;
491
+	ti,dual-emac-pvid = <2>;
387
492
 };
388
493
 
389
-&davinci_mdio {
494
+&davinci_mdio_sw {
390
495
 	dp83867_0: ethernet-phy@2 {
391
496
 		reg = <2>;
392
497
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
..
..
@@ -412,6 +517,23 @@
412
517
 
413
518
 &usb2_phy2 {
414
519
 	phy-supply = <&ldo3_reg>;
520
+};
521
+
522
+&dss {
523
+	status = "okay";
524
+	vdda_video-supply = <&ldo5_reg>;
525
+};
526
+
527
+&hdmi {
528
+	status = "okay";
529
+
530
+	vdda-supply = <&ldo1_reg>;
531
+
532
+	port {
533
+		hdmi_out: endpoint {
534
+			remote-endpoint = <&tpd12s015_in>;
535
+		};
536
+	};
415
537
 };
416
538
 
417
539
 &qspi {
..
..
@@ -450,3 +572,31 @@
450
572
 		max-bitrate = <5000000>;
451
573
 	};
452
574
 };
575
+
576
+&csi2_0 {
577
+	csi2_phy0: endpoint {
578
+		remote-endpoint = <&csi2_cam0>;
579
+		clock-lanes = <0>;
580
+		data-lanes = <1 2>;
581
+	};
582
+};
583
+
584
+&ipu2 {
585
+	status = "okay";
586
+	memory-region = <&ipu2_cma_pool>;
587
+};
588
+
589
+&ipu1 {
590
+	status = "okay";
591
+	memory-region = <&ipu1_cma_pool>;
592
+};
593
+
594
+&dsp1 {
595
+	status = "okay";
596
+	memory-region = <&dsp1_cma_pool>;
597
+};
598
+
599
+&dsp2 {
600
+	status = "okay";
601
+	memory-region = <&dsp2_cma_pool>;
602
+};