| .. | .. |
|---|
| 122 | 122 | ranges = <0 0xf7000000 0x1000000>; |
|---|
| 123 | 123 | interrupt-parent = <&gic>; |
|---|
| 124 | 124 | |
|---|
| 125 | | - sdhci0: sdhci@ab0000 { |
|---|
| 125 | + sdhci0: mmc@ab0000 { |
|---|
| 126 | 126 | compatible = "mrvl,pxav3-mmc"; |
|---|
| 127 | 127 | reg = <0xab0000 0x200>; |
|---|
| 128 | 128 | clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; |
|---|
| .. | .. |
|---|
| 131 | 131 | status = "disabled"; |
|---|
| 132 | 132 | }; |
|---|
| 133 | 133 | |
|---|
| 134 | | - sdhci1: sdhci@ab0800 { |
|---|
| 134 | + sdhci1: mmc@ab0800 { |
|---|
| 135 | 135 | compatible = "mrvl,pxav3-mmc"; |
|---|
| 136 | 136 | reg = <0xab0800 0x200>; |
|---|
| 137 | 137 | clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; |
|---|
| .. | .. |
|---|
| 140 | 140 | status = "disabled"; |
|---|
| 141 | 141 | }; |
|---|
| 142 | 142 | |
|---|
| 143 | | - sdhci2: sdhci@ab1000 { |
|---|
| 143 | + sdhci2: mmc@ab1000 { |
|---|
| 144 | 144 | compatible = "mrvl,pxav3-mmc"; |
|---|
| 145 | 145 | reg = <0xab1000 0x200>; |
|---|
| 146 | 146 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
|---|
| .. | .. |
|---|
| 149 | 149 | status = "disabled"; |
|---|
| 150 | 150 | }; |
|---|
| 151 | 151 | |
|---|
| 152 | | - l2: l2-cache-controller@ac0000 { |
|---|
| 152 | + l2: cache-controller@ac0000 { |
|---|
| 153 | 153 | compatible = "arm,pl310-cache"; |
|---|
| 154 | 154 | reg = <0xac0000 0x1000>; |
|---|
| 155 | 155 | cache-unified; |
|---|