| .. | .. |
|---|
| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
|---|
| 1 | 2 | /* |
|---|
| 2 | 3 | * QLogic Fibre Channel HBA Driver |
|---|
| 3 | 4 | * Copyright (c) 2003-2014 QLogic Corporation |
|---|
| 4 | | - * |
|---|
| 5 | | - * See LICENSE.qla2xxx for copyright and licensing details. |
|---|
| 6 | 5 | */ |
|---|
| 7 | 6 | |
|---|
| 8 | 7 | #include <linux/vmalloc.h> |
|---|
| .. | .. |
|---|
| 559 | 558 | /* |
|---|
| 560 | 559 | * Address and length are byte address |
|---|
| 561 | 560 | */ |
|---|
| 562 | | -uint8_t * |
|---|
| 563 | | -qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
|---|
| 561 | +void * |
|---|
| 562 | +qla8044_read_optrom_data(struct scsi_qla_host *vha, void *buf, |
|---|
| 564 | 563 | uint32_t offset, uint32_t length) |
|---|
| 565 | 564 | { |
|---|
| 566 | 565 | scsi_block_requests(vha->host); |
|---|
| 567 | | - if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4) |
|---|
| 566 | + if (qla8044_read_flash_data(vha, buf, offset, length / 4) |
|---|
| 568 | 567 | != QLA_SUCCESS) { |
|---|
| 569 | 568 | ql_log(ql_log_warn, vha, 0xb08d, |
|---|
| 570 | 569 | "%s: Failed to read from flash\n", |
|---|
| .. | .. |
|---|
| 660 | 659 | qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr, |
|---|
| 661 | 660 | int duration, uint32_t test_mask, uint32_t test_result) |
|---|
| 662 | 661 | { |
|---|
| 663 | | - uint32_t value; |
|---|
| 662 | + uint32_t value = 0; |
|---|
| 664 | 663 | int timeout_error; |
|---|
| 665 | 664 | uint8_t retries; |
|---|
| 666 | 665 | int ret_val = QLA_SUCCESS; |
|---|
| .. | .. |
|---|
| 1441 | 1440 | if (idc_ctrl & GRACEFUL_RESET_BIT1) { |
|---|
| 1442 | 1441 | qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, |
|---|
| 1443 | 1442 | (idc_ctrl & ~GRACEFUL_RESET_BIT1)); |
|---|
| 1444 | | - ha->fw_dumped = 0; |
|---|
| 1443 | + ha->fw_dumped = false; |
|---|
| 1445 | 1444 | } |
|---|
| 1446 | 1445 | |
|---|
| 1447 | 1446 | dev_ready: |
|---|
| .. | .. |
|---|
| 2810 | 2809 | |
|---|
| 2811 | 2810 | #define ISP8044_PEX_DMA_ENGINE_INDEX 8 |
|---|
| 2812 | 2811 | #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000 |
|---|
| 2813 | | -#define ISP8044_PEX_DMA_NUM_OFFSET 0x10000 |
|---|
| 2812 | +#define ISP8044_PEX_DMA_NUM_OFFSET 0x10000UL |
|---|
| 2814 | 2813 | #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0 |
|---|
| 2815 | 2814 | #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04 |
|---|
| 2816 | 2815 | #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08 |
|---|
| .. | .. |
|---|
| 2965 | 2964 | |
|---|
| 2966 | 2965 | /* Prepare: Write pex-dma descriptor to MS memory. */ |
|---|
| 2967 | 2966 | rval = qla8044_ms_mem_write_128b(vha, |
|---|
| 2968 | | - m_hdr->desc_card_addr, (void *)&dma_desc, |
|---|
| 2967 | + m_hdr->desc_card_addr, (uint32_t *)&dma_desc, |
|---|
| 2969 | 2968 | (sizeof(struct qla8044_pex_dma_descriptor)/16)); |
|---|
| 2970 | 2969 | if (rval) { |
|---|
| 2971 | 2970 | ql_log(ql_log_warn, vha, 0xb14a, |
|---|
| .. | .. |
|---|
| 2987 | 2986 | read_size += chunk_size; |
|---|
| 2988 | 2987 | } |
|---|
| 2989 | 2988 | |
|---|
| 2990 | | - *d_ptr = (void *)data_ptr; |
|---|
| 2989 | + *d_ptr = (uint32_t *)data_ptr; |
|---|
| 2991 | 2990 | |
|---|
| 2992 | 2991 | error_exit: |
|---|
| 2993 | 2992 | if (rdmem_buffer) |
|---|
| .. | .. |
|---|
| 3007 | 3006 | uint16_t count; |
|---|
| 3008 | 3007 | uint32_t poll, mask, modify_mask; |
|---|
| 3009 | 3008 | uint32_t wait_count = 0; |
|---|
| 3010 | | - |
|---|
| 3011 | 3009 | uint32_t *data_ptr = *d_ptr; |
|---|
| 3012 | | - |
|---|
| 3013 | 3010 | struct qla8044_minidump_entry_rddfe *rddfe; |
|---|
| 3011 | + |
|---|
| 3014 | 3012 | rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr; |
|---|
| 3015 | 3013 | |
|---|
| 3016 | 3014 | addr1 = rddfe->addr_1; |
|---|
| .. | .. |
|---|
| 3250 | 3248 | goto md_failed; |
|---|
| 3251 | 3249 | } |
|---|
| 3252 | 3250 | |
|---|
| 3253 | | - ha->fw_dumped = 0; |
|---|
| 3251 | + ha->fw_dumped = false; |
|---|
| 3254 | 3252 | |
|---|
| 3255 | 3253 | if (!ha->md_tmplt_hdr || !ha->md_dump) { |
|---|
| 3256 | 3254 | ql_log(ql_log_warn, vha, 0xb10e, |
|---|
| .. | .. |
|---|
| 3471 | 3469 | ql_log(ql_log_info, vha, 0xb110, |
|---|
| 3472 | 3470 | "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", |
|---|
| 3473 | 3471 | vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); |
|---|
| 3474 | | - ha->fw_dumped = 1; |
|---|
| 3472 | + ha->fw_dumped = true; |
|---|
| 3475 | 3473 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); |
|---|
| 3476 | 3474 | |
|---|
| 3477 | 3475 | |
|---|
| .. | .. |
|---|
| 3488 | 3486 | struct qla_hw_data *ha = vha->hw; |
|---|
| 3489 | 3487 | |
|---|
| 3490 | 3488 | if (!qla8044_collect_md_data(vha)) { |
|---|
| 3491 | | - ha->fw_dumped = 1; |
|---|
| 3489 | + ha->fw_dumped = true; |
|---|
| 3492 | 3490 | ha->prev_minidump_failed = 0; |
|---|
| 3493 | 3491 | } else { |
|---|
| 3494 | 3492 | ql_log(ql_log_fatal, vha, 0xb0db, |
|---|
| .. | .. |
|---|
| 3797 | 3795 | } |
|---|
| 3798 | 3796 | |
|---|
| 3799 | 3797 | int |
|---|
| 3800 | | -qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
|---|
| 3798 | +qla8044_write_optrom_data(struct scsi_qla_host *vha, void *buf, |
|---|
| 3801 | 3799 | uint32_t offset, uint32_t length) |
|---|
| 3802 | 3800 | { |
|---|
| 3803 | 3801 | int rval = QLA_FUNCTION_FAILED, i, burst_iter_count; |
|---|
| .. | .. |
|---|
| 3878 | 3876 | #define PF_BITS_MASK (0xF << 16) |
|---|
| 3879 | 3877 | /** |
|---|
| 3880 | 3878 | * qla8044_intr_handler() - Process interrupts for the ISP8044 |
|---|
| 3881 | | - * @irq: |
|---|
| 3879 | + * @irq: interrupt number |
|---|
| 3882 | 3880 | * @dev_id: SCSI driver HA context |
|---|
| 3883 | 3881 | * |
|---|
| 3884 | 3882 | * Called by system whenever the host adapter generates an interrupt. |
|---|
| .. | .. |
|---|
| 3896 | 3894 | unsigned long flags; |
|---|
| 3897 | 3895 | unsigned long iter; |
|---|
| 3898 | 3896 | uint32_t stat; |
|---|
| 3899 | | - uint16_t mb[4]; |
|---|
| 3897 | + uint16_t mb[8]; |
|---|
| 3900 | 3898 | uint32_t leg_int_ptr = 0, pf_bit; |
|---|
| 3901 | 3899 | |
|---|
| 3902 | 3900 | rsp = (struct rsp_que *) dev_id; |
|---|
| .. | .. |
|---|
| 3947 | 3945 | spin_lock_irqsave(&ha->hardware_lock, flags); |
|---|
| 3948 | 3946 | for (iter = 1; iter--; ) { |
|---|
| 3949 | 3947 | |
|---|
| 3950 | | - if (RD_REG_DWORD(®->host_int)) { |
|---|
| 3951 | | - stat = RD_REG_DWORD(®->host_status); |
|---|
| 3948 | + if (rd_reg_dword(®->host_int)) { |
|---|
| 3949 | + stat = rd_reg_dword(®->host_status); |
|---|
| 3952 | 3950 | if ((stat & HSRX_RISC_INT) == 0) |
|---|
| 3953 | 3951 | break; |
|---|
| 3954 | 3952 | |
|---|
| .. | .. |
|---|
| 3962 | 3960 | break; |
|---|
| 3963 | 3961 | case 0x12: |
|---|
| 3964 | 3962 | mb[0] = MSW(stat); |
|---|
| 3965 | | - mb[1] = RD_REG_WORD(®->mailbox_out[1]); |
|---|
| 3966 | | - mb[2] = RD_REG_WORD(®->mailbox_out[2]); |
|---|
| 3967 | | - mb[3] = RD_REG_WORD(®->mailbox_out[3]); |
|---|
| 3963 | + mb[1] = rd_reg_word(®->mailbox_out[1]); |
|---|
| 3964 | + mb[2] = rd_reg_word(®->mailbox_out[2]); |
|---|
| 3965 | + mb[3] = rd_reg_word(®->mailbox_out[3]); |
|---|
| 3968 | 3966 | qla2x00_async_event(vha, rsp, mb); |
|---|
| 3969 | 3967 | break; |
|---|
| 3970 | 3968 | case 0x13: |
|---|
| .. | .. |
|---|
| 3977 | 3975 | break; |
|---|
| 3978 | 3976 | } |
|---|
| 3979 | 3977 | } |
|---|
| 3980 | | - WRT_REG_DWORD(®->host_int, 0); |
|---|
| 3978 | + wrt_reg_dword(®->host_int, 0); |
|---|
| 3981 | 3979 | } |
|---|
| 3982 | 3980 | |
|---|
| 3983 | 3981 | qla2x00_handle_mbx_completion(ha, status); |
|---|
| .. | .. |
|---|
| 4071 | 4069 | } |
|---|
| 4072 | 4070 | |
|---|
| 4073 | 4071 | void |
|---|
| 4074 | | -qla8044_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
|---|
| 4072 | +qla8044_fw_dump(scsi_qla_host_t *vha) |
|---|
| 4075 | 4073 | { |
|---|
| 4076 | 4074 | struct qla_hw_data *ha = vha->hw; |
|---|
| 4077 | 4075 | |
|---|