~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,8 +1,7 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* QLogic Fibre Channel HBA Driver
3	4	* Copyright (c) 2003-2014 QLogic Corporation
4		- *
5		- * See LICENSE.qla2xxx for copyright and licensing details.
6	5	*/
7	6
8	7	/*
..	..	@@ -11,26 +10,19 @@
11	10	* ----------------------------------------------------------------------
12	11	* \| Level \| Last Value Used \| Holes \|
13	12	* ----------------------------------------------------------------------
14		- * \| Module Init and Probe \| 0x0193 \| 0x0146 \|
15		- * \| \| \| 0x015b-0x0160 \|
16		- * \| \| \| 0x016e \|
17		- * \| Mailbox commands \| 0x1206 \| 0x11a2-0x11ff \|
18		- * \| Device Discovery \| 0x2134 \| 0x210e-0x2116 \|
19		- * \| \| \| 0x211a \|
	13	+ * \| Module Init and Probe \| 0x0199 \| \|
	14	+ * \| Mailbox commands \| 0x1206 \| 0x11a5-0x11ff \|
	15	+ * \| Device Discovery \| 0x2134 \| 0x210e-0x2115 \|
20	16	* \| \| \| 0x211c-0x2128 \|
21		- * \| \| \| 0x212a-0x2130 \|
	17	+ * \| \| \| 0x212c-0x2134 \|
22	18	* \| Queue Command and IO tracing \| 0x3074 \| 0x300b \|
23	19	* \| \| \| 0x3027-0x3028 \|
24	20	* \| \| \| 0x303d-0x3041 \|
25		- * \| \| \| 0x302d,0x3033 \|
	21	+ * \| \| \| 0x302e,0x3033 \|
26	22	* \| \| \| 0x3036,0x3038 \|
27	23	* \| \| \| 0x303a \|
28	24	* \| DPC Thread \| 0x4023 \| 0x4002,0x4013 \|
29		- * \| Async Events \| 0x5090 \| 0x502b-0x502f \|
30		- * \| \| \| 0x5047 \|
31		- * \| \| \| 0x5084,0x5075 \|
32		- * \| \| \| 0x503d,0x5044 \|
33		- * \| \| \| 0x505f \|
	25	+ * \| Async Events \| 0x509c \| \|
34	26	* \| Timer Routines \| 0x6012 \| \|
35	27	* \| User Space Interactions \| 0x70e3 \| 0x7018,0x702e \|
36	28	* \| \| \| 0x7020,0x7024 \|
..	..	@@ -73,6 +65,8 @@
73	65	#include "qla_def.h"
74	66
75	67	#include <linux/delay.h>
	68	+#define CREATE_TRACE_POINTS
	69	+#include <trace/events/qla.h>
76	70
77	71	static uint32_t ql_dbg_offset = 0x800;
78	72
..	..	@@ -111,162 +105,175 @@
111	105	qla27xx_dump_mpi_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
112	106	uint32_t ram_dwords, void **nxt)
113	107	{
114		- int rval;
115		- uint32_t cnt, stat, timer, dwords, idx;
116		- uint16_t mb0;
117	108	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
118	109	dma_addr_t dump_dma = ha->gid_list_dma;
119		- uint32_t dump = (uint32_t )ha->gid_list;
	110	+ uint32_t chunk = (uint32_t )ha->gid_list;
	111	+ uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
	112	+ uint32_t stat;
	113	+ ulong i, j, timer = 6000000;
	114	+ int rval = QLA_FUNCTION_FAILED;
	115	+ scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
120	116
121		- rval = QLA_SUCCESS;
122		- mb0 = 0;
123		-
124		- WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
125	117	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
126	118
127		- dwords = qla2x00_gid_list_size(ha) / 4;
128		- for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
129		- cnt += dwords, addr += dwords) {
130		- if (cnt + dwords > ram_dwords)
131		- dwords = ram_dwords - cnt;
	119	+ if (qla_pci_disconnected(vha, reg))
	120	+ return rval;
132	121
133		- WRT_REG_WORD(&reg->mailbox1, LSW(addr));
134		- WRT_REG_WORD(&reg->mailbox8, MSW(addr));
	122	+ for (i = 0; i < ram_dwords; i += dwords, addr += dwords) {
	123	+ if (i + dwords > ram_dwords)
	124	+ dwords = ram_dwords - i;
135	125
136		- WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
137		- WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
138		- WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
139		- WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
	126	+ wrt_reg_word(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
	127	+ wrt_reg_word(&reg->mailbox1, LSW(addr));
	128	+ wrt_reg_word(&reg->mailbox8, MSW(addr));
140	129
141		- WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
142		- WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
	130	+ wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma)));
	131	+ wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma)));
	132	+ wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma)));
	133	+ wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma)));
143	134
144		- WRT_REG_WORD(&reg->mailbox9, 0);
145		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
	135	+ wrt_reg_word(&reg->mailbox4, MSW(dwords));
	136	+ wrt_reg_word(&reg->mailbox5, LSW(dwords));
	137	+
	138	+ wrt_reg_word(&reg->mailbox9, 0);
	139	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);
146	140
147	141	ha->flags.mbox_int = 0;
148		- for (timer = 6000000; timer; timer--) {
	142	+ while (timer--) {
	143	+ udelay(5);
	144	+
	145	+ if (qla_pci_disconnected(vha, reg))
	146	+ return rval;
	147	+
	148	+ stat = rd_reg_dword(&reg->host_status);
149	149	/* Check for pending interrupts. */
150		- stat = RD_REG_DWORD(&reg->host_status);
151		- if (stat & HSRX_RISC_INT) {
152		- stat &= 0xff;
	150	+ if (!(stat & HSRX_RISC_INT))
	151	+ continue;
153	152
154		- if (stat == 0x1 \|\| stat == 0x2 \|\|
155		- stat == 0x10 \|\| stat == 0x11) {
156		- set_bit(MBX_INTERRUPT,
157		- &ha->mbx_cmd_flags);
158		-
159		- mb0 = RD_REG_WORD(&reg->mailbox0);
160		- RD_REG_WORD(&reg->mailbox1);
161		-
162		- WRT_REG_DWORD(&reg->hccr,
163		- HCCRX_CLR_RISC_INT);
164		- RD_REG_DWORD(&reg->hccr);
165		- break;
166		- }
	153	+ stat &= 0xff;
	154	+ if (stat != 0x1 && stat != 0x2 &&
	155	+ stat != 0x10 && stat != 0x11) {
167	156
168	157	/* Clear this intr; it wasn't a mailbox intr */
169		- WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
170		- RD_REG_DWORD(&reg->hccr);
	158	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);
	159	+ rd_reg_dword(&reg->hccr);
	160	+ continue;
171	161	}
172		- udelay(5);
	162	+
	163	+ set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
	164	+ rval = rd_reg_word(&reg->mailbox0) & MBS_MASK;
	165	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);
	166	+ rd_reg_dword(&reg->hccr);
	167	+ break;
173	168	}
174	169	ha->flags.mbox_int = 1;
	170	+ *nxt = ram + i;
175	171
176		- if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
177		- rval = mb0 & MBS_MASK;
178		- for (idx = 0; idx < dwords; idx++)
179		- ram[cnt + idx] = IS_QLA27XX(ha) ?
180		- le32_to_cpu(dump[idx]) : swab32(dump[idx]);
181		- } else {
182		- rval = QLA_FUNCTION_FAILED;
	172	+ if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
	173	+ /* no interrupt, timed out*/
	174	+ return rval;
	175	+ }
	176	+ if (rval) {
	177	+ /* error completion status */
	178	+ return rval;
	179	+ }
	180	+ for (j = 0; j < dwords; j++) {
	181	+ ram[i + j] =
	182	+ (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) ?
	183	+ chunk[j] : swab32(chunk[j]);
183	184	}
184	185	}
185	186
186		- *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
187		- return rval;
	187	+ *nxt = ram + i;
	188	+ return QLA_SUCCESS;
188	189	}
189	190
190	191	int
191		-qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
192		- uint32_t ram_dwords, void **nxt)
	192	+qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, __be32 ram,
	193	+ uint32_t ram_dwords, void **nxt)
193	194	{
194		- int rval;
195		- uint32_t cnt, stat, timer, dwords, idx;
196		- uint16_t mb0;
	195	+ int rval = QLA_FUNCTION_FAILED;
197	196	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
198	197	dma_addr_t dump_dma = ha->gid_list_dma;
199		- uint32_t dump = (uint32_t )ha->gid_list;
	198	+ uint32_t chunk = (uint32_t )ha->gid_list;
	199	+ uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
	200	+ uint32_t stat;
	201	+ ulong i, j, timer = 6000000;
	202	+ scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
200	203
201		- rval = QLA_SUCCESS;
202		- mb0 = 0;
203		-
204		- WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
205	204	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
206	205
207		- dwords = qla2x00_gid_list_size(ha) / 4;
208		- for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
209		- cnt += dwords, addr += dwords) {
210		- if (cnt + dwords > ram_dwords)
211		- dwords = ram_dwords - cnt;
	206	+ if (qla_pci_disconnected(vha, reg))
	207	+ return rval;
212	208
213		- WRT_REG_WORD(&reg->mailbox1, LSW(addr));
214		- WRT_REG_WORD(&reg->mailbox8, MSW(addr));
	209	+ for (i = 0; i < ram_dwords; i += dwords, addr += dwords) {
	210	+ if (i + dwords > ram_dwords)
	211	+ dwords = ram_dwords - i;
215	212
216		- WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
217		- WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
218		- WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
219		- WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
	213	+ wrt_reg_word(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
	214	+ wrt_reg_word(&reg->mailbox1, LSW(addr));
	215	+ wrt_reg_word(&reg->mailbox8, MSW(addr));
	216	+ wrt_reg_word(&reg->mailbox10, 0);
220	217
221		- WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
222		- WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
223		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
	218	+ wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma)));
	219	+ wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma)));
	220	+ wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma)));
	221	+ wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma)));
	222	+
	223	+ wrt_reg_word(&reg->mailbox4, MSW(dwords));
	224	+ wrt_reg_word(&reg->mailbox5, LSW(dwords));
	225	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);
224	226
225	227	ha->flags.mbox_int = 0;
226		- for (timer = 6000000; timer; timer--) {
227		- /* Check for pending interrupts. */
228		- stat = RD_REG_DWORD(&reg->host_status);
229		- if (stat & HSRX_RISC_INT) {
230		- stat &= 0xff;
231		-
232		- if (stat == 0x1 \|\| stat == 0x2 \|\|
233		- stat == 0x10 \|\| stat == 0x11) {
234		- set_bit(MBX_INTERRUPT,
235		- &ha->mbx_cmd_flags);
236		-
237		- mb0 = RD_REG_WORD(&reg->mailbox0);
238		-
239		- WRT_REG_DWORD(&reg->hccr,
240		- HCCRX_CLR_RISC_INT);
241		- RD_REG_DWORD(&reg->hccr);
242		- break;
243		- }
244		-
245		- /* Clear this intr; it wasn't a mailbox intr */
246		- WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
247		- RD_REG_DWORD(&reg->hccr);
248		- }
	228	+ while (timer--) {
249	229	udelay(5);
	230	+ if (qla_pci_disconnected(vha, reg))
	231	+ return rval;
	232	+
	233	+ stat = rd_reg_dword(&reg->host_status);
	234	+ /* Check for pending interrupts. */
	235	+ if (!(stat & HSRX_RISC_INT))
	236	+ continue;
	237	+
	238	+ stat &= 0xff;
	239	+ if (stat != 0x1 && stat != 0x2 &&
	240	+ stat != 0x10 && stat != 0x11) {
	241	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);
	242	+ rd_reg_dword(&reg->hccr);
	243	+ continue;
	244	+ }
	245	+
	246	+ set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
	247	+ rval = rd_reg_word(&reg->mailbox0) & MBS_MASK;
	248	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);
	249	+ rd_reg_dword(&reg->hccr);
	250	+ break;
250	251	}
251	252	ha->flags.mbox_int = 1;
	253	+ *nxt = ram + i;
252	254
253		- if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
254		- rval = mb0 & MBS_MASK;
255		- for (idx = 0; idx < dwords; idx++)
256		- ram[cnt + idx] = IS_QLA27XX(ha) ?
257		- le32_to_cpu(dump[idx]) : swab32(dump[idx]);
258		- } else {
259		- rval = QLA_FUNCTION_FAILED;
	255	+ if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
	256	+ /* no interrupt, timed out*/
	257	+ return rval;
	258	+ }
	259	+ if (rval) {
	260	+ /* error completion status */
	261	+ return rval;
	262	+ }
	263	+ for (j = 0; j < dwords; j++) {
	264	+ ram[i + j] = (__force __be32)
	265	+ ((IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) ?
	266	+ chunk[j] : swab32(chunk[j]));
260	267	}
261	268	}
262	269
263		- *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
264		- return rval;
	270	+ *nxt = ram + i;
	271	+ return QLA_SUCCESS;
265	272	}
266	273
267	274	static int
268		-qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
269		- uint32_t cram_size, void **nxt)
	275	+qla24xx_dump_memory(struct qla_hw_data ha, __be32 code_ram,
	276	+ uint32_t cram_size, void **nxt)
270	277	{
271	278	int rval;
272	279
..	..	@@ -286,16 +293,16 @@
286	293	return rval;
287	294	}
288	295
289		-static uint32_t *
	296	+static __be32 *
290	297	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
291		- uint32_t count, uint32_t *buf)
	298	+ uint32_t count, __be32 *buf)
292	299	{
293		- uint32_t __iomem *dmp_reg;
	300	+ __le32 __iomem *dmp_reg;
294	301
295		- WRT_REG_DWORD(&reg->iobase_addr, iobase);
	302	+ wrt_reg_dword(&reg->iobase_addr, iobase);
296	303	dmp_reg = &reg->iobase_window;
297	304	for ( ; count--; dmp_reg++)
298		- *buf++ = htonl(RD_REG_DWORD(dmp_reg));
	305	+ *buf++ = htonl(rd_reg_dword(dmp_reg));
299	306
300	307	return buf;
301	308	}
..	..	@@ -303,11 +310,11 @@
303	310	void
304	311	qla24xx_pause_risc(struct device_reg_24xx __iomem reg, struct qla_hw_data ha)
305	312	{
306		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
	313	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_PAUSE);
307	314
308	315	/* 100 usec delay is sufficient enough for hardware to pause RISC */
309	316	udelay(100);
310		- if (RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED)
	317	+ if (rd_reg_dword(&reg->host_status) & HSRX_RISC_PAUSED)
311	318	set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
312	319	}
313	320
..	..	@@ -324,17 +331,17 @@
324	331	* Driver can proceed with the reset sequence after waiting
325	332	* for a timeout period.
326	333	*/
327		- WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
	334	+ wrt_reg_dword(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
328	335	for (cnt = 0; cnt < 30000; cnt++) {
329		- if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
	336	+ if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
330	337	break;
331	338
332	339	udelay(10);
333	340	}
334		- if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
	341	+ if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
335	342	set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
336	343
337		- WRT_REG_DWORD(&reg->ctrl_status,
	344	+ wrt_reg_dword(&reg->ctrl_status,
338	345	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
339	346	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
340	347
..	..	@@ -342,19 +349,19 @@
342	349
343	350	/* Wait for soft-reset to complete. */
344	351	for (cnt = 0; cnt < 30000; cnt++) {
345		- if ((RD_REG_DWORD(&reg->ctrl_status) &
	352	+ if ((rd_reg_dword(&reg->ctrl_status) &
346	353	CSRX_ISP_SOFT_RESET) == 0)
347	354	break;
348	355
349	356	udelay(10);
350	357	}
351		- if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
	358	+ if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
352	359	set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
353	360
354		- WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
355		- RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
	361	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_RESET);
	362	+ rd_reg_dword(&reg->hccr); /* PCI Posting. */
356	363
357		- for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
	364	+ for (cnt = 10000; rd_reg_word(&reg->mailbox0) != 0 &&
358	365	rval == QLA_SUCCESS; cnt--) {
359	366	if (cnt)
360	367	udelay(10);
..	..	@@ -368,7 +375,7 @@
368	375	}
369	376
370	377	static int
371		-qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
	378	+qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, __be16 ram,
372	379	uint32_t ram_words, void **nxt)
373	380	{
374	381	int rval;
..	..	@@ -376,7 +383,7 @@
376	383	uint16_t mb0;
377	384	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
378	385	dma_addr_t dump_dma = ha->gid_list_dma;
379		- uint16_t dump = (uint16_t )ha->gid_list;
	386	+ __le16 dump = (__force __le16 )ha->gid_list;
380	387
381	388	rval = QLA_SUCCESS;
382	389	mb0 = 0;
..	..	@@ -399,11 +406,11 @@
399	406	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
400	407
401	408	WRT_MAILBOX_REG(ha, reg, 4, words);
402		- WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
	409	+ wrt_reg_word(&reg->hccr, HCCR_SET_HOST_INT);
403	410
404	411	for (timer = 6000000; timer; timer--) {
405	412	/* Check for pending interrupts. */
406		- stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
	413	+ stat = rd_reg_dword(&reg->u.isp2300.host_status);
407	414	if (stat & HSR_RISC_INT) {
408	415	stat &= 0xff;
409	416
..	..	@@ -414,10 +421,10 @@
414	421	mb0 = RD_MAILBOX_REG(ha, reg, 0);
415	422
416	423	/* Release mailbox registers. */
417		- WRT_REG_WORD(&reg->semaphore, 0);
418		- WRT_REG_WORD(&reg->hccr,
	424	+ wrt_reg_word(&reg->semaphore, 0);
	425	+ wrt_reg_word(&reg->hccr,
419	426	HCCR_CLR_RISC_INT);
420		- RD_REG_WORD(&reg->hccr);
	427	+ rd_reg_word(&reg->hccr);
421	428	break;
422	429	} else if (stat == 0x10 \|\| stat == 0x11) {
423	430	set_bit(MBX_INTERRUPT,
..	..	@@ -425,15 +432,15 @@
425	432
426	433	mb0 = RD_MAILBOX_REG(ha, reg, 0);
427	434
428		- WRT_REG_WORD(&reg->hccr,
	435	+ wrt_reg_word(&reg->hccr,
429	436	HCCR_CLR_RISC_INT);
430		- RD_REG_WORD(&reg->hccr);
	437	+ rd_reg_word(&reg->hccr);
431	438	break;
432	439	}
433	440
434	441	/* clear this intr; it wasn't a mailbox intr */
435		- WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
436		- RD_REG_WORD(&reg->hccr);
	442	+ wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT);
	443	+ rd_reg_word(&reg->hccr);
437	444	}
438	445	udelay(5);
439	446	}
..	..	@@ -441,24 +448,25 @@
441	448	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
442	449	rval = mb0 & MBS_MASK;
443	450	for (idx = 0; idx < words; idx++)
444		- ram[cnt + idx] = swab16(dump[idx]);
	451	+ ram[cnt + idx] =
	452	+ cpu_to_be16(le16_to_cpu(dump[idx]));
445	453	} else {
446	454	rval = QLA_FUNCTION_FAILED;
447	455	}
448	456	}
449	457
450		- *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
	458	+ *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
451	459	return rval;
452	460	}
453	461
454	462	static inline void
455	463	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
456		- uint16_t *buf)
	464	+ __be16 *buf)
457	465	{
458		- uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
	466	+ __le16 __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
459	467
460	468	for ( ; count--; dmp_reg++)
461		- *buf++ = htons(RD_REG_WORD(dmp_reg));
	469	+ *buf++ = htons(rd_reg_word(dmp_reg));
462	470	}
463	471
464	472	static inline void *
..	..	@@ -472,10 +480,10 @@
472	480	}
473	481
474	482	static inline void *
475		-qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	483	+qla25xx_copy_fce(struct qla_hw_data ha, void ptr, __be32 **last_chain)
476	484	{
477	485	uint32_t cnt;
478		- uint32_t *iter_reg;
	486	+ __be32 *iter_reg;
479	487	struct qla2xxx_fce_chain *fcec = ptr;
480	488
481	489	if (!ha->fce)
..	..	@@ -499,7 +507,7 @@
499	507	}
500	508
501	509	static inline void *
502		-qla25xx_copy_exlogin(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	510	+qla25xx_copy_exlogin(struct qla_hw_data ha, void ptr, __be32 **last_chain)
503	511	{
504	512	struct qla2xxx_offld_chain *c = ptr;
505	513
..	..	@@ -517,11 +525,11 @@
517	525	ptr += sizeof(struct qla2xxx_offld_chain);
518	526	memcpy(ptr, ha->exlogin_buf, ha->exlogin_size);
519	527
520		- return (char *)ptr + cpu_to_be32(c->size);
	528	+ return (char *)ptr + be32_to_cpu(c->size);
521	529	}
522	530
523	531	static inline void *
524		-qla81xx_copy_exchoffld(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	532	+qla81xx_copy_exchoffld(struct qla_hw_data ha, void ptr, __be32 **last_chain)
525	533	{
526	534	struct qla2xxx_offld_chain *c = ptr;
527	535
..	..	@@ -539,12 +547,12 @@
539	547	ptr += sizeof(struct qla2xxx_offld_chain);
540	548	memcpy(ptr, ha->exchoffld_buf, ha->exchoffld_size);
541	549
542		- return (char *)ptr + cpu_to_be32(c->size);
	550	+ return (char *)ptr + be32_to_cpu(c->size);
543	551	}
544	552
545	553	static inline void *
546	554	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
547		- uint32_t **last_chain)
	555	+ __be32 **last_chain)
548	556	{
549	557	struct qla2xxx_mqueue_chain *q;
550	558	struct qla2xxx_mqueue_header *qh;
..	..	@@ -591,7 +599,7 @@
591	599	}
592	600
593	601	static inline void *
594		-qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	602	+qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, __be32 **last_chain)
595	603	{
596	604	struct qla2xxx_mqueue_chain *q;
597	605	struct qla2xxx_mqueue_header *qh;
..	..	@@ -662,14 +670,15 @@
662	670	}
663	671
664	672	static inline void *
665		-qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	673	+qla25xx_copy_mq(struct qla_hw_data ha, void ptr, __be32 **last_chain)
666	674	{
667	675	uint32_t cnt, que_idx;
668	676	uint8_t que_cnt;
669	677	struct qla2xxx_mq_chain *mq = ptr;
670	678	device_reg_t *reg;
671	679
672		- if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	680	+ if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\|
	681	+ IS_QLA28XX(ha))
673	682	return ptr;
674	683
675	684	mq = ptr;
..	..	@@ -684,13 +693,13 @@
684	693	reg = ISP_QUE_REG(ha, cnt);
685	694	que_idx = cnt * 4;
686	695	mq->qregs[que_idx] =
687		- htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
	696	+ htonl(rd_reg_dword(&reg->isp25mq.req_q_in));
688	697	mq->qregs[que_idx+1] =
689		- htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
	698	+ htonl(rd_reg_dword(&reg->isp25mq.req_q_out));
690	699	mq->qregs[que_idx+2] =
691		- htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
	700	+ htonl(rd_reg_dword(&reg->isp25mq.rsp_q_in));
692	701	mq->qregs[que_idx+3] =
693		- htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
	702	+ htonl(rd_reg_dword(&reg->isp25mq.rsp_q_out));
694	703	}
695	704
696	705	return ptr + sizeof(struct qla2xxx_mq_chain);
..	..	@@ -705,45 +714,47 @@
705	714	ql_log(ql_log_warn, vha, 0xd000,
706	715	"Failed to dump firmware (%x), dump status flags (0x%lx).\n",
707	716	rval, ha->fw_dump_cap_flags);
708		- ha->fw_dumped = 0;
	717	+ ha->fw_dumped = false;
709	718	} else {
710	719	ql_log(ql_log_info, vha, 0xd001,
711	720	"Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n",
712	721	vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
713		- ha->fw_dumped = 1;
	722	+ ha->fw_dumped = true;
714	723	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
715	724	}
	725	+}
	726	+
	727	+void qla2xxx_dump_fw(scsi_qla_host_t *vha)
	728	+{
	729	+ unsigned long flags;
	730	+
	731	+ spin_lock_irqsave(&vha->hw->hardware_lock, flags);
	732	+ vha->hw->isp_ops->fw_dump(vha);
	733	+ spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
716	734	}
717	735
718	736	/**
719	737	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
720	738	* @vha: HA context
721		- * @hardware_locked: Called with the hardware_lock
722	739	*/
723	740	void
724		-qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	741	+qla2300_fw_dump(scsi_qla_host_t *vha)
725	742	{
726	743	int rval;
727	744	uint32_t cnt;
728	745	struct qla_hw_data *ha = vha->hw;
729	746	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
730		- uint16_t __iomem *dmp_reg;
731		- unsigned long flags;
	747	+ __le16 __iomem *dmp_reg;
732	748	struct qla2300_fw_dump *fw;
733	749	void *nxt;
734	750	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
735	751
736		- flags = 0;
737		-
738		-#ifndef __CHECKER__
739		- if (!hardware_locked)
740		- spin_lock_irqsave(&ha->hardware_lock, flags);
741		-#endif
	752	+ lockdep_assert_held(&ha->hardware_lock);
742	753
743	754	if (!ha->fw_dump) {
744	755	ql_log(ql_log_warn, vha, 0xd002,
745	756	"No buffer available for dump.\n");
746		- goto qla2300_fw_dump_failed;
	757	+ return;
747	758	}
748	759
749	760	if (ha->fw_dumped) {
..	..	@@ -751,19 +762,19 @@
751	762	"Firmware has been previously dumped (%p) "
752	763	"-- ignoring request.\n",
753	764	ha->fw_dump);
754		- goto qla2300_fw_dump_failed;
	765	+ return;
755	766	}
756	767	fw = &ha->fw_dump->isp.isp23;
757	768	qla2xxx_prep_dump(ha, ha->fw_dump);
758	769
759	770	rval = QLA_SUCCESS;
760		- fw->hccr = htons(RD_REG_WORD(&reg->hccr));
	771	+ fw->hccr = htons(rd_reg_word(&reg->hccr));
761	772
762	773	/* Pause RISC. */
763		- WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
	774	+ wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);
764	775	if (IS_QLA2300(ha)) {
765	776	for (cnt = 30000;
766		- (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
	777	+ (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
767	778	rval == QLA_SUCCESS; cnt--) {
768	779	if (cnt)
769	780	udelay(100);
..	..	@@ -771,74 +782,74 @@
771	782	rval = QLA_FUNCTION_TIMEOUT;
772	783	}
773	784	} else {
774		- RD_REG_WORD(&reg->hccr); /* PCI Posting. */
	785	+ rd_reg_word(&reg->hccr); /* PCI Posting. */
775	786	udelay(10);
776	787	}
777	788
778	789	if (rval == QLA_SUCCESS) {
779	790	dmp_reg = &reg->flash_address;
780		- for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++)
781		- fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	791	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->pbiu_reg); cnt++, dmp_reg++)
	792	+ fw->pbiu_reg[cnt] = htons(rd_reg_word(dmp_reg));
782	793
783	794	dmp_reg = &reg->u.isp2300.req_q_in;
784		- for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2;
	795	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_host_reg);
785	796	cnt++, dmp_reg++)
786		- fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	797	+ fw->risc_host_reg[cnt] = htons(rd_reg_word(dmp_reg));
787	798
788	799	dmp_reg = &reg->u.isp2300.mailbox0;
789		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2;
	800	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg);
790	801	cnt++, dmp_reg++)
791		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	802	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(dmp_reg));
792	803
793		- WRT_REG_WORD(&reg->ctrl_status, 0x40);
	804	+ wrt_reg_word(&reg->ctrl_status, 0x40);
794	805	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
795	806
796		- WRT_REG_WORD(&reg->ctrl_status, 0x50);
	807	+ wrt_reg_word(&reg->ctrl_status, 0x50);
797	808	qla2xxx_read_window(reg, 48, fw->dma_reg);
798	809
799		- WRT_REG_WORD(&reg->ctrl_status, 0x00);
	810	+ wrt_reg_word(&reg->ctrl_status, 0x00);
800	811	dmp_reg = &reg->risc_hw;
801		- for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2;
	812	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_hdw_reg);
802	813	cnt++, dmp_reg++)
803		- fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	814	+ fw->risc_hdw_reg[cnt] = htons(rd_reg_word(dmp_reg));
804	815
805		- WRT_REG_WORD(&reg->pcr, 0x2000);
	816	+ wrt_reg_word(&reg->pcr, 0x2000);
806	817	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
807	818
808		- WRT_REG_WORD(&reg->pcr, 0x2200);
	819	+ wrt_reg_word(&reg->pcr, 0x2200);
809	820	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
810	821
811		- WRT_REG_WORD(&reg->pcr, 0x2400);
	822	+ wrt_reg_word(&reg->pcr, 0x2400);
812	823	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
813	824
814		- WRT_REG_WORD(&reg->pcr, 0x2600);
	825	+ wrt_reg_word(&reg->pcr, 0x2600);
815	826	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
816	827
817		- WRT_REG_WORD(&reg->pcr, 0x2800);
	828	+ wrt_reg_word(&reg->pcr, 0x2800);
818	829	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
819	830
820		- WRT_REG_WORD(&reg->pcr, 0x2A00);
	831	+ wrt_reg_word(&reg->pcr, 0x2A00);
821	832	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
822	833
823		- WRT_REG_WORD(&reg->pcr, 0x2C00);
	834	+ wrt_reg_word(&reg->pcr, 0x2C00);
824	835	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
825	836
826		- WRT_REG_WORD(&reg->pcr, 0x2E00);
	837	+ wrt_reg_word(&reg->pcr, 0x2E00);
827	838	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
828	839
829		- WRT_REG_WORD(&reg->ctrl_status, 0x10);
	840	+ wrt_reg_word(&reg->ctrl_status, 0x10);
830	841	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
831	842
832		- WRT_REG_WORD(&reg->ctrl_status, 0x20);
	843	+ wrt_reg_word(&reg->ctrl_status, 0x20);
833	844	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
834	845
835		- WRT_REG_WORD(&reg->ctrl_status, 0x30);
	846	+ wrt_reg_word(&reg->ctrl_status, 0x30);
836	847	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
837	848
838	849	/* Reset RISC. */
839		- WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
	850	+ wrt_reg_word(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
840	851	for (cnt = 0; cnt < 30000; cnt++) {
841		- if ((RD_REG_WORD(&reg->ctrl_status) &
	852	+ if ((rd_reg_word(&reg->ctrl_status) &
842	853	CSR_ISP_SOFT_RESET) == 0)
843	854	break;
844	855
..	..	@@ -859,12 +870,12 @@
859	870	/* Get RISC SRAM. */
860	871	if (rval == QLA_SUCCESS)
861	872	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
862		- sizeof(fw->risc_ram) / 2, &nxt);
	873	+ ARRAY_SIZE(fw->risc_ram), &nxt);
863	874
864	875	/* Get stack SRAM. */
865	876	if (rval == QLA_SUCCESS)
866	877	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
867		- sizeof(fw->stack_ram) / 2, &nxt);
	878	+ ARRAY_SIZE(fw->stack_ram), &nxt);
868	879
869	880	/* Get data SRAM. */
870	881	if (rval == QLA_SUCCESS)
..	..	@@ -875,48 +886,31 @@
875	886	qla2xxx_copy_queues(ha, nxt);
876	887
877	888	qla2xxx_dump_post_process(base_vha, rval);
878		-
879		-qla2300_fw_dump_failed:
880		-#ifndef __CHECKER__
881		- if (!hardware_locked)
882		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
883		-#else
884		- ;
885		-#endif
886	889	}
887	890
888	891	/**
889	892	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
890	893	* @vha: HA context
891		- * @hardware_locked: Called with the hardware_lock
892	894	*/
893	895	void
894		-qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	896	+qla2100_fw_dump(scsi_qla_host_t *vha)
895	897	{
896	898	int rval;
897	899	uint32_t cnt, timer;
898		- uint16_t risc_address;
899		- uint16_t mb0, mb2;
	900	+ uint16_t risc_address = 0;
	901	+ uint16_t mb0 = 0, mb2 = 0;
900	902	struct qla_hw_data *ha = vha->hw;
901	903	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
902		- uint16_t __iomem *dmp_reg;
903		- unsigned long flags;
	904	+ __le16 __iomem *dmp_reg;
904	905	struct qla2100_fw_dump *fw;
905	906	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
906	907
907		- risc_address = 0;
908		- mb0 = mb2 = 0;
909		- flags = 0;
910		-
911		-#ifndef __CHECKER__
912		- if (!hardware_locked)
913		- spin_lock_irqsave(&ha->hardware_lock, flags);
914		-#endif
	908	+ lockdep_assert_held(&ha->hardware_lock);
915	909
916	910	if (!ha->fw_dump) {
917	911	ql_log(ql_log_warn, vha, 0xd004,
918	912	"No buffer available for dump.\n");
919		- goto qla2100_fw_dump_failed;
	913	+ return;
920	914	}
921	915
922	916	if (ha->fw_dumped) {
..	..	@@ -924,17 +918,17 @@
924	918	"Firmware has been previously dumped (%p) "
925	919	"-- ignoring request.\n",
926	920	ha->fw_dump);
927		- goto qla2100_fw_dump_failed;
	921	+ return;
928	922	}
929	923	fw = &ha->fw_dump->isp.isp21;
930	924	qla2xxx_prep_dump(ha, ha->fw_dump);
931	925
932	926	rval = QLA_SUCCESS;
933		- fw->hccr = htons(RD_REG_WORD(&reg->hccr));
	927	+ fw->hccr = htons(rd_reg_word(&reg->hccr));
934	928
935	929	/* Pause RISC. */
936		- WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
937		- for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
	930	+ wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);
	931	+ for (cnt = 30000; (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
938	932	rval == QLA_SUCCESS; cnt--) {
939	933	if (cnt)
940	934	udelay(100);
..	..	@@ -943,61 +937,61 @@
943	937	}
944	938	if (rval == QLA_SUCCESS) {
945	939	dmp_reg = &reg->flash_address;
946		- for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++)
947		- fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	940	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->pbiu_reg); cnt++, dmp_reg++)
	941	+ fw->pbiu_reg[cnt] = htons(rd_reg_word(dmp_reg));
948	942
949	943	dmp_reg = &reg->u.isp2100.mailbox0;
950	944	for (cnt = 0; cnt < ha->mbx_count; cnt++, dmp_reg++) {
951	945	if (cnt == 8)
952	946	dmp_reg = &reg->u_end.isp2200.mailbox8;
953	947
954		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	948	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(dmp_reg));
955	949	}
956	950
957	951	dmp_reg = &reg->u.isp2100.unused_2[0];
958		- for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++, dmp_reg++)
959		- fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	952	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->dma_reg); cnt++, dmp_reg++)
	953	+ fw->dma_reg[cnt] = htons(rd_reg_word(dmp_reg));
960	954
961		- WRT_REG_WORD(&reg->ctrl_status, 0x00);
	955	+ wrt_reg_word(&reg->ctrl_status, 0x00);
962	956	dmp_reg = &reg->risc_hw;
963		- for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++, dmp_reg++)
964		- fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	957	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_hdw_reg); cnt++, dmp_reg++)
	958	+ fw->risc_hdw_reg[cnt] = htons(rd_reg_word(dmp_reg));
965	959
966		- WRT_REG_WORD(&reg->pcr, 0x2000);
	960	+ wrt_reg_word(&reg->pcr, 0x2000);
967	961	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
968	962
969		- WRT_REG_WORD(&reg->pcr, 0x2100);
	963	+ wrt_reg_word(&reg->pcr, 0x2100);
970	964	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
971	965
972		- WRT_REG_WORD(&reg->pcr, 0x2200);
	966	+ wrt_reg_word(&reg->pcr, 0x2200);
973	967	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
974	968
975		- WRT_REG_WORD(&reg->pcr, 0x2300);
	969	+ wrt_reg_word(&reg->pcr, 0x2300);
976	970	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
977	971
978		- WRT_REG_WORD(&reg->pcr, 0x2400);
	972	+ wrt_reg_word(&reg->pcr, 0x2400);
979	973	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
980	974
981		- WRT_REG_WORD(&reg->pcr, 0x2500);
	975	+ wrt_reg_word(&reg->pcr, 0x2500);
982	976	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
983	977
984		- WRT_REG_WORD(&reg->pcr, 0x2600);
	978	+ wrt_reg_word(&reg->pcr, 0x2600);
985	979	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
986	980
987		- WRT_REG_WORD(&reg->pcr, 0x2700);
	981	+ wrt_reg_word(&reg->pcr, 0x2700);
988	982	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
989	983
990		- WRT_REG_WORD(&reg->ctrl_status, 0x10);
	984	+ wrt_reg_word(&reg->ctrl_status, 0x10);
991	985	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
992	986
993		- WRT_REG_WORD(&reg->ctrl_status, 0x20);
	987	+ wrt_reg_word(&reg->ctrl_status, 0x20);
994	988	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
995	989
996		- WRT_REG_WORD(&reg->ctrl_status, 0x30);
	990	+ wrt_reg_word(&reg->ctrl_status, 0x30);
997	991	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
998	992
999	993	/* Reset the ISP. */
1000		- WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
	994	+ wrt_reg_word(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1001	995	}
1002	996
1003	997	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
..	..	@@ -1010,11 +1004,11 @@
1010	1004
1011	1005	/* Pause RISC. */
1012	1006	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
1013		- (RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
	1007	+ (rd_reg_word(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
1014	1008
1015		- WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
	1009	+ wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);
1016	1010	for (cnt = 30000;
1017		- (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
	1011	+ (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
1018	1012	rval == QLA_SUCCESS; cnt--) {
1019	1013	if (cnt)
1020	1014	udelay(100);
..	..	@@ -1024,13 +1018,13 @@
1024	1018	if (rval == QLA_SUCCESS) {
1025	1019	/* Set memory configuration and timing. */
1026	1020	if (IS_QLA2100(ha))
1027		- WRT_REG_WORD(&reg->mctr, 0xf1);
	1021	+ wrt_reg_word(&reg->mctr, 0xf1);
1028	1022	else
1029		- WRT_REG_WORD(&reg->mctr, 0xf2);
1030		- RD_REG_WORD(&reg->mctr); /* PCI Posting. */
	1023	+ wrt_reg_word(&reg->mctr, 0xf2);
	1024	+ rd_reg_word(&reg->mctr); /* PCI Posting. */
1031	1025
1032	1026	/* Release RISC. */
1033		- WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
	1027	+ wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);
1034	1028	}
1035	1029	}
1036	1030
..	..	@@ -1040,29 +1034,29 @@
1040	1034	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
1041	1035	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1042	1036	}
1043		- for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
	1037	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_ram) && rval == QLA_SUCCESS;
1044	1038	cnt++, risc_address++) {
1045	1039	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
1046		- WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
	1040	+ wrt_reg_word(&reg->hccr, HCCR_SET_HOST_INT);
1047	1041
1048	1042	for (timer = 6000000; timer != 0; timer--) {
1049	1043	/* Check for pending interrupts. */
1050		- if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
1051		- if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
	1044	+ if (rd_reg_word(&reg->istatus) & ISR_RISC_INT) {
	1045	+ if (rd_reg_word(&reg->semaphore) & BIT_0) {
1052	1046	set_bit(MBX_INTERRUPT,
1053	1047	&ha->mbx_cmd_flags);
1054	1048
1055	1049	mb0 = RD_MAILBOX_REG(ha, reg, 0);
1056	1050	mb2 = RD_MAILBOX_REG(ha, reg, 2);
1057	1051
1058		- WRT_REG_WORD(&reg->semaphore, 0);
1059		- WRT_REG_WORD(&reg->hccr,
	1052	+ wrt_reg_word(&reg->semaphore, 0);
	1053	+ wrt_reg_word(&reg->hccr,
1060	1054	HCCR_CLR_RISC_INT);
1061		- RD_REG_WORD(&reg->hccr);
	1055	+ rd_reg_word(&reg->hccr);
1062	1056	break;
1063	1057	}
1064		- WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1065		- RD_REG_WORD(&reg->hccr);
	1058	+ wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT);
	1059	+ rd_reg_word(&reg->hccr);
1066	1060	}
1067	1061	udelay(5);
1068	1062	}
..	..	@@ -1076,51 +1070,38 @@
1076	1070	}
1077	1071
1078	1072	if (rval == QLA_SUCCESS)
1079		- qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
	1073	+ qla2xxx_copy_queues(ha, &fw->queue_dump[0]);
1080	1074
1081	1075	qla2xxx_dump_post_process(base_vha, rval);
1082		-
1083		-qla2100_fw_dump_failed:
1084		-#ifndef __CHECKER__
1085		- if (!hardware_locked)
1086		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
1087		-#else
1088		- ;
1089		-#endif
1090	1076	}
1091	1077
1092	1078	void
1093		-qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	1079	+qla24xx_fw_dump(scsi_qla_host_t *vha)
1094	1080	{
1095	1081	int rval;
1096	1082	uint32_t cnt;
1097	1083	struct qla_hw_data *ha = vha->hw;
1098	1084	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1099		- uint32_t __iomem *dmp_reg;
1100		- uint32_t *iter_reg;
1101		- uint16_t __iomem *mbx_reg;
1102		- unsigned long flags;
	1085	+ __le32 __iomem *dmp_reg;
	1086	+ __be32 *iter_reg;
	1087	+ __le16 __iomem *mbx_reg;
1103	1088	struct qla24xx_fw_dump *fw;
1104	1089	void *nxt;
1105	1090	void *nxt_chain;
1106		- uint32_t *last_chain = NULL;
	1091	+ __be32 *last_chain = NULL;
1107	1092	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
	1093	+
	1094	+ lockdep_assert_held(&ha->hardware_lock);
1108	1095
1109	1096	if (IS_P3P_TYPE(ha))
1110	1097	return;
1111	1098
1112		- flags = 0;
1113	1099	ha->fw_dump_cap_flags = 0;
1114		-
1115		-#ifndef __CHECKER__
1116		- if (!hardware_locked)
1117		- spin_lock_irqsave(&ha->hardware_lock, flags);
1118		-#endif
1119	1100
1120	1101	if (!ha->fw_dump) {
1121	1102	ql_log(ql_log_warn, vha, 0xd006,
1122	1103	"No buffer available for dump.\n");
1123		- goto qla24xx_fw_dump_failed;
	1104	+ return;
1124	1105	}
1125	1106
1126	1107	if (ha->fw_dumped) {
..	..	@@ -1128,13 +1109,13 @@
1128	1109	"Firmware has been previously dumped (%p) "
1129	1110	"-- ignoring request.\n",
1130	1111	ha->fw_dump);
1131		- goto qla24xx_fw_dump_failed;
	1112	+ return;
1132	1113	}
1133	1114	QLA_FW_STOPPED(ha);
1134	1115	fw = &ha->fw_dump->isp.isp24;
1135	1116	qla2xxx_prep_dump(ha, ha->fw_dump);
1136	1117
1137		- fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
	1118	+ fw->host_status = htonl(rd_reg_dword(&reg->host_status));
1138	1119
1139	1120	/*
1140	1121	* Pause RISC. No need to track timeout, as resetting the chip
..	..	@@ -1144,41 +1125,41 @@
1144	1125
1145	1126	/* Host interface registers. */
1146	1127	dmp_reg = &reg->flash_addr;
1147		- for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
1148		- fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
	1128	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
	1129	+ fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
1149	1130
1150	1131	/* Disable interrupts. */
1151		- WRT_REG_DWORD(&reg->ictrl, 0);
1152		- RD_REG_DWORD(&reg->ictrl);
	1132	+ wrt_reg_dword(&reg->ictrl, 0);
	1133	+ rd_reg_dword(&reg->ictrl);
1153	1134
1154	1135	/* Shadow registers. */
1155		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1156		- RD_REG_DWORD(&reg->iobase_addr);
1157		- WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1158		- fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1136	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	1137	+ rd_reg_dword(&reg->iobase_addr);
	1138	+ wrt_reg_dword(&reg->iobase_select, 0xB0000000);
	1139	+ fw->shadow_reg[0] = htonl(rd_reg_dword(&reg->iobase_sdata));
1159	1140
1160		- WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1161		- fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1141	+ wrt_reg_dword(&reg->iobase_select, 0xB0100000);
	1142	+ fw->shadow_reg[1] = htonl(rd_reg_dword(&reg->iobase_sdata));
1162	1143
1163		- WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1164		- fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1144	+ wrt_reg_dword(&reg->iobase_select, 0xB0200000);
	1145	+ fw->shadow_reg[2] = htonl(rd_reg_dword(&reg->iobase_sdata));
1165	1146
1166		- WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1167		- fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1147	+ wrt_reg_dword(&reg->iobase_select, 0xB0300000);
	1148	+ fw->shadow_reg[3] = htonl(rd_reg_dword(&reg->iobase_sdata));
1168	1149
1169		- WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1170		- fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1150	+ wrt_reg_dword(&reg->iobase_select, 0xB0400000);
	1151	+ fw->shadow_reg[4] = htonl(rd_reg_dword(&reg->iobase_sdata));
1171	1152
1172		- WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1173		- fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1153	+ wrt_reg_dword(&reg->iobase_select, 0xB0500000);
	1154	+ fw->shadow_reg[5] = htonl(rd_reg_dword(&reg->iobase_sdata));
1174	1155
1175		- WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1176		- fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1156	+ wrt_reg_dword(&reg->iobase_select, 0xB0600000);
	1157	+ fw->shadow_reg[6] = htonl(rd_reg_dword(&reg->iobase_sdata));
1177	1158
1178	1159	/* Mailbox registers. */
1179	1160	mbx_reg = &reg->mailbox0;
1180		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
1181		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
	1161	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
	1162	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
1182	1163
1183	1164	/* Transfer sequence registers. */
1184	1165	iter_reg = fw->xseq_gp_reg;
..	..	@@ -1217,19 +1198,19 @@
1217	1198	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1218	1199	dmp_reg = &reg->iobase_q;
1219	1200	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1220		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1201	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1221	1202
1222	1203	iter_reg = fw->resp0_dma_reg;
1223	1204	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1224	1205	dmp_reg = &reg->iobase_q;
1225	1206	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1226		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1207	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1227	1208
1228	1209	iter_reg = fw->req1_dma_reg;
1229	1210	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1230	1211	dmp_reg = &reg->iobase_q;
1231	1212	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1232		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1213	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1233	1214
1234	1215	/* Transmit DMA registers. */
1235	1216	iter_reg = fw->xmt0_dma_reg;
..	..	@@ -1338,44 +1319,31 @@
1338	1319
1339	1320	qla24xx_fw_dump_failed_0:
1340	1321	qla2xxx_dump_post_process(base_vha, rval);
1341		-
1342		-qla24xx_fw_dump_failed:
1343		-#ifndef __CHECKER__
1344		- if (!hardware_locked)
1345		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
1346		-#else
1347		- ;
1348		-#endif
1349	1322	}
1350	1323
1351	1324	void
1352		-qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	1325	+qla25xx_fw_dump(scsi_qla_host_t *vha)
1353	1326	{
1354	1327	int rval;
1355	1328	uint32_t cnt;
1356	1329	struct qla_hw_data *ha = vha->hw;
1357	1330	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1358		- uint32_t __iomem *dmp_reg;
1359		- uint32_t *iter_reg;
1360		- uint16_t __iomem *mbx_reg;
1361		- unsigned long flags;
	1331	+ __le32 __iomem *dmp_reg;
	1332	+ __be32 *iter_reg;
	1333	+ __le16 __iomem *mbx_reg;
1362	1334	struct qla25xx_fw_dump *fw;
1363	1335	void nxt, nxt_chain;
1364		- uint32_t *last_chain = NULL;
	1336	+ __be32 *last_chain = NULL;
1365	1337	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1366	1338
1367		- flags = 0;
1368		- ha->fw_dump_cap_flags = 0;
	1339	+ lockdep_assert_held(&ha->hardware_lock);
1369	1340
1370		-#ifndef __CHECKER__
1371		- if (!hardware_locked)
1372		- spin_lock_irqsave(&ha->hardware_lock, flags);
1373		-#endif
	1341	+ ha->fw_dump_cap_flags = 0;
1374	1342
1375	1343	if (!ha->fw_dump) {
1376	1344	ql_log(ql_log_warn, vha, 0xd008,
1377	1345	"No buffer available for dump.\n");
1378		- goto qla25xx_fw_dump_failed;
	1346	+ return;
1379	1347	}
1380	1348
1381	1349	if (ha->fw_dumped) {
..	..	@@ -1383,14 +1351,14 @@
1383	1351	"Firmware has been previously dumped (%p) "
1384	1352	"-- ignoring request.\n",
1385	1353	ha->fw_dump);
1386		- goto qla25xx_fw_dump_failed;
	1354	+ return;
1387	1355	}
1388	1356	QLA_FW_STOPPED(ha);
1389	1357	fw = &ha->fw_dump->isp.isp25;
1390	1358	qla2xxx_prep_dump(ha, ha->fw_dump);
1391	1359	ha->fw_dump->version = htonl(2);
1392	1360
1393		- fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
	1361	+ fw->host_status = htonl(rd_reg_dword(&reg->host_status));
1394	1362
1395	1363	/*
1396	1364	* Pause RISC. No need to track timeout, as resetting the chip
..	..	@@ -1404,73 +1372,73 @@
1404	1372	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1405	1373
1406	1374	/* PCIe registers. */
1407		- WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1408		- RD_REG_DWORD(&reg->iobase_addr);
1409		- WRT_REG_DWORD(&reg->iobase_window, 0x01);
	1375	+ wrt_reg_dword(&reg->iobase_addr, 0x7C00);
	1376	+ rd_reg_dword(&reg->iobase_addr);
	1377	+ wrt_reg_dword(&reg->iobase_window, 0x01);
1410	1378	dmp_reg = &reg->iobase_c4;
1411		- fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
	1379	+ fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
1412	1380	dmp_reg++;
1413		- fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
	1381	+ fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
1414	1382	dmp_reg++;
1415		- fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1416		- fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
	1383	+ fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
	1384	+ fw->pcie_regs[3] = htonl(rd_reg_dword(&reg->iobase_window));
1417	1385
1418		- WRT_REG_DWORD(&reg->iobase_window, 0x00);
1419		- RD_REG_DWORD(&reg->iobase_window);
	1386	+ wrt_reg_dword(&reg->iobase_window, 0x00);
	1387	+ rd_reg_dword(&reg->iobase_window);
1420	1388
1421	1389	/* Host interface registers. */
1422	1390	dmp_reg = &reg->flash_addr;
1423		- for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
1424		- fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
	1391	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
	1392	+ fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
1425	1393
1426	1394	/* Disable interrupts. */
1427		- WRT_REG_DWORD(&reg->ictrl, 0);
1428		- RD_REG_DWORD(&reg->ictrl);
	1395	+ wrt_reg_dword(&reg->ictrl, 0);
	1396	+ rd_reg_dword(&reg->ictrl);
1429	1397
1430	1398	/* Shadow registers. */
1431		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1432		- RD_REG_DWORD(&reg->iobase_addr);
1433		- WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1434		- fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1399	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	1400	+ rd_reg_dword(&reg->iobase_addr);
	1401	+ wrt_reg_dword(&reg->iobase_select, 0xB0000000);
	1402	+ fw->shadow_reg[0] = htonl(rd_reg_dword(&reg->iobase_sdata));
1435	1403
1436		- WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1437		- fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1404	+ wrt_reg_dword(&reg->iobase_select, 0xB0100000);
	1405	+ fw->shadow_reg[1] = htonl(rd_reg_dword(&reg->iobase_sdata));
1438	1406
1439		- WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1440		- fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1407	+ wrt_reg_dword(&reg->iobase_select, 0xB0200000);
	1408	+ fw->shadow_reg[2] = htonl(rd_reg_dword(&reg->iobase_sdata));
1441	1409
1442		- WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1443		- fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1410	+ wrt_reg_dword(&reg->iobase_select, 0xB0300000);
	1411	+ fw->shadow_reg[3] = htonl(rd_reg_dword(&reg->iobase_sdata));
1444	1412
1445		- WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1446		- fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1413	+ wrt_reg_dword(&reg->iobase_select, 0xB0400000);
	1414	+ fw->shadow_reg[4] = htonl(rd_reg_dword(&reg->iobase_sdata));
1447	1415
1448		- WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1449		- fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1416	+ wrt_reg_dword(&reg->iobase_select, 0xB0500000);
	1417	+ fw->shadow_reg[5] = htonl(rd_reg_dword(&reg->iobase_sdata));
1450	1418
1451		- WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1452		- fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1419	+ wrt_reg_dword(&reg->iobase_select, 0xB0600000);
	1420	+ fw->shadow_reg[6] = htonl(rd_reg_dword(&reg->iobase_sdata));
1453	1421
1454		- WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1455		- fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1422	+ wrt_reg_dword(&reg->iobase_select, 0xB0700000);
	1423	+ fw->shadow_reg[7] = htonl(rd_reg_dword(&reg->iobase_sdata));
1456	1424
1457		- WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1458		- fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1425	+ wrt_reg_dword(&reg->iobase_select, 0xB0800000);
	1426	+ fw->shadow_reg[8] = htonl(rd_reg_dword(&reg->iobase_sdata));
1459	1427
1460		- WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1461		- fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1428	+ wrt_reg_dword(&reg->iobase_select, 0xB0900000);
	1429	+ fw->shadow_reg[9] = htonl(rd_reg_dword(&reg->iobase_sdata));
1462	1430
1463		- WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1464		- fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1431	+ wrt_reg_dword(&reg->iobase_select, 0xB0A00000);
	1432	+ fw->shadow_reg[10] = htonl(rd_reg_dword(&reg->iobase_sdata));
1465	1433
1466	1434	/* RISC I/O register. */
1467		- WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1468		- fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
	1435	+ wrt_reg_dword(&reg->iobase_addr, 0x0010);
	1436	+ fw->risc_io_reg = htonl(rd_reg_dword(&reg->iobase_window));
1469	1437
1470	1438	/* Mailbox registers. */
1471	1439	mbx_reg = &reg->mailbox0;
1472		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
1473		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
	1440	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
	1441	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
1474	1442
1475	1443	/* Transfer sequence registers. */
1476	1444	iter_reg = fw->xseq_gp_reg;
..	..	@@ -1534,19 +1502,19 @@
1534	1502	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1535	1503	dmp_reg = &reg->iobase_q;
1536	1504	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1537		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1505	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1538	1506
1539	1507	iter_reg = fw->resp0_dma_reg;
1540	1508	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1541	1509	dmp_reg = &reg->iobase_q;
1542	1510	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1543		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1511	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1544	1512
1545	1513	iter_reg = fw->req1_dma_reg;
1546	1514	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1547	1515	dmp_reg = &reg->iobase_q;
1548	1516	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1549		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1517	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1550	1518
1551	1519	/* Transmit DMA registers. */
1552	1520	iter_reg = fw->xmt0_dma_reg;
..	..	@@ -1664,44 +1632,31 @@
1664	1632
1665	1633	qla25xx_fw_dump_failed_0:
1666	1634	qla2xxx_dump_post_process(base_vha, rval);
1667		-
1668		-qla25xx_fw_dump_failed:
1669		-#ifndef __CHECKER__
1670		- if (!hardware_locked)
1671		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
1672		-#else
1673		- ;
1674		-#endif
1675	1635	}
1676	1636
1677	1637	void
1678		-qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	1638	+qla81xx_fw_dump(scsi_qla_host_t *vha)
1679	1639	{
1680	1640	int rval;
1681	1641	uint32_t cnt;
1682	1642	struct qla_hw_data *ha = vha->hw;
1683	1643	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1684		- uint32_t __iomem *dmp_reg;
1685		- uint32_t *iter_reg;
1686		- uint16_t __iomem *mbx_reg;
1687		- unsigned long flags;
	1644	+ __le32 __iomem *dmp_reg;
	1645	+ __be32 *iter_reg;
	1646	+ __le16 __iomem *mbx_reg;
1688	1647	struct qla81xx_fw_dump *fw;
1689	1648	void nxt, nxt_chain;
1690		- uint32_t *last_chain = NULL;
	1649	+ __be32 *last_chain = NULL;
1691	1650	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1692	1651
1693		- flags = 0;
1694		- ha->fw_dump_cap_flags = 0;
	1652	+ lockdep_assert_held(&ha->hardware_lock);
1695	1653
1696		-#ifndef __CHECKER__
1697		- if (!hardware_locked)
1698		- spin_lock_irqsave(&ha->hardware_lock, flags);
1699		-#endif
	1654	+ ha->fw_dump_cap_flags = 0;
1700	1655
1701	1656	if (!ha->fw_dump) {
1702	1657	ql_log(ql_log_warn, vha, 0xd00a,
1703	1658	"No buffer available for dump.\n");
1704		- goto qla81xx_fw_dump_failed;
	1659	+ return;
1705	1660	}
1706	1661
1707	1662	if (ha->fw_dumped) {
..	..	@@ -1709,12 +1664,12 @@
1709	1664	"Firmware has been previously dumped (%p) "
1710	1665	"-- ignoring request.\n",
1711	1666	ha->fw_dump);
1712		- goto qla81xx_fw_dump_failed;
	1667	+ return;
1713	1668	}
1714	1669	fw = &ha->fw_dump->isp.isp81;
1715	1670	qla2xxx_prep_dump(ha, ha->fw_dump);
1716	1671
1717		- fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
	1672	+ fw->host_status = htonl(rd_reg_dword(&reg->host_status));
1718	1673
1719	1674	/*
1720	1675	* Pause RISC. No need to track timeout, as resetting the chip
..	..	@@ -1728,73 +1683,73 @@
1728	1683	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1729	1684
1730	1685	/* PCIe registers. */
1731		- WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1732		- RD_REG_DWORD(&reg->iobase_addr);
1733		- WRT_REG_DWORD(&reg->iobase_window, 0x01);
	1686	+ wrt_reg_dword(&reg->iobase_addr, 0x7C00);
	1687	+ rd_reg_dword(&reg->iobase_addr);
	1688	+ wrt_reg_dword(&reg->iobase_window, 0x01);
1734	1689	dmp_reg = &reg->iobase_c4;
1735		- fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
	1690	+ fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
1736	1691	dmp_reg++;
1737		- fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
	1692	+ fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
1738	1693	dmp_reg++;
1739		- fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1740		- fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
	1694	+ fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
	1695	+ fw->pcie_regs[3] = htonl(rd_reg_dword(&reg->iobase_window));
1741	1696
1742		- WRT_REG_DWORD(&reg->iobase_window, 0x00);
1743		- RD_REG_DWORD(&reg->iobase_window);
	1697	+ wrt_reg_dword(&reg->iobase_window, 0x00);
	1698	+ rd_reg_dword(&reg->iobase_window);
1744	1699
1745	1700	/* Host interface registers. */
1746	1701	dmp_reg = &reg->flash_addr;
1747		- for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
1748		- fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
	1702	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
	1703	+ fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
1749	1704
1750	1705	/* Disable interrupts. */
1751		- WRT_REG_DWORD(&reg->ictrl, 0);
1752		- RD_REG_DWORD(&reg->ictrl);
	1706	+ wrt_reg_dword(&reg->ictrl, 0);
	1707	+ rd_reg_dword(&reg->ictrl);
1753	1708
1754	1709	/* Shadow registers. */
1755		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1756		- RD_REG_DWORD(&reg->iobase_addr);
1757		- WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1758		- fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1710	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	1711	+ rd_reg_dword(&reg->iobase_addr);
	1712	+ wrt_reg_dword(&reg->iobase_select, 0xB0000000);
	1713	+ fw->shadow_reg[0] = htonl(rd_reg_dword(&reg->iobase_sdata));
1759	1714
1760		- WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1761		- fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1715	+ wrt_reg_dword(&reg->iobase_select, 0xB0100000);
	1716	+ fw->shadow_reg[1] = htonl(rd_reg_dword(&reg->iobase_sdata));
1762	1717
1763		- WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1764		- fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1718	+ wrt_reg_dword(&reg->iobase_select, 0xB0200000);
	1719	+ fw->shadow_reg[2] = htonl(rd_reg_dword(&reg->iobase_sdata));
1765	1720
1766		- WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1767		- fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1721	+ wrt_reg_dword(&reg->iobase_select, 0xB0300000);
	1722	+ fw->shadow_reg[3] = htonl(rd_reg_dword(&reg->iobase_sdata));
1768	1723
1769		- WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1770		- fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1724	+ wrt_reg_dword(&reg->iobase_select, 0xB0400000);
	1725	+ fw->shadow_reg[4] = htonl(rd_reg_dword(&reg->iobase_sdata));
1771	1726
1772		- WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1773		- fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1727	+ wrt_reg_dword(&reg->iobase_select, 0xB0500000);
	1728	+ fw->shadow_reg[5] = htonl(rd_reg_dword(&reg->iobase_sdata));
1774	1729
1775		- WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1776		- fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1730	+ wrt_reg_dword(&reg->iobase_select, 0xB0600000);
	1731	+ fw->shadow_reg[6] = htonl(rd_reg_dword(&reg->iobase_sdata));
1777	1732
1778		- WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1779		- fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1733	+ wrt_reg_dword(&reg->iobase_select, 0xB0700000);
	1734	+ fw->shadow_reg[7] = htonl(rd_reg_dword(&reg->iobase_sdata));
1780	1735
1781		- WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1782		- fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1736	+ wrt_reg_dword(&reg->iobase_select, 0xB0800000);
	1737	+ fw->shadow_reg[8] = htonl(rd_reg_dword(&reg->iobase_sdata));
1783	1738
1784		- WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1785		- fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1739	+ wrt_reg_dword(&reg->iobase_select, 0xB0900000);
	1740	+ fw->shadow_reg[9] = htonl(rd_reg_dword(&reg->iobase_sdata));
1786	1741
1787		- WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1788		- fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1742	+ wrt_reg_dword(&reg->iobase_select, 0xB0A00000);
	1743	+ fw->shadow_reg[10] = htonl(rd_reg_dword(&reg->iobase_sdata));
1789	1744
1790	1745	/* RISC I/O register. */
1791		- WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1792		- fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
	1746	+ wrt_reg_dword(&reg->iobase_addr, 0x0010);
	1747	+ fw->risc_io_reg = htonl(rd_reg_dword(&reg->iobase_window));
1793	1748
1794	1749	/* Mailbox registers. */
1795	1750	mbx_reg = &reg->mailbox0;
1796		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
1797		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
	1751	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
	1752	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
1798	1753
1799	1754	/* Transfer sequence registers. */
1800	1755	iter_reg = fw->xseq_gp_reg;
..	..	@@ -1858,19 +1813,19 @@
1858	1813	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1859	1814	dmp_reg = &reg->iobase_q;
1860	1815	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1861		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1816	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1862	1817
1863	1818	iter_reg = fw->resp0_dma_reg;
1864	1819	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1865	1820	dmp_reg = &reg->iobase_q;
1866	1821	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1867		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1822	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1868	1823
1869	1824	iter_reg = fw->req1_dma_reg;
1870	1825	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1871	1826	dmp_reg = &reg->iobase_q;
1872	1827	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1873		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1828	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1874	1829
1875	1830	/* Transmit DMA registers. */
1876	1831	iter_reg = fw->xmt0_dma_reg;
..	..	@@ -1992,57 +1947,44 @@
1992	1947
1993	1948	qla81xx_fw_dump_failed_0:
1994	1949	qla2xxx_dump_post_process(base_vha, rval);
1995		-
1996		-qla81xx_fw_dump_failed:
1997		-#ifndef __CHECKER__
1998		- if (!hardware_locked)
1999		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
2000		-#else
2001		- ;
2002		-#endif
2003	1950	}
2004	1951
2005	1952	void
2006		-qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	1953	+qla83xx_fw_dump(scsi_qla_host_t *vha)
2007	1954	{
2008	1955	int rval;
2009	1956	uint32_t cnt;
2010	1957	struct qla_hw_data *ha = vha->hw;
2011	1958	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2012		- uint32_t __iomem *dmp_reg;
2013		- uint32_t *iter_reg;
2014		- uint16_t __iomem *mbx_reg;
2015		- unsigned long flags;
	1959	+ __le32 __iomem *dmp_reg;
	1960	+ __be32 *iter_reg;
	1961	+ __le16 __iomem *mbx_reg;
2016	1962	struct qla83xx_fw_dump *fw;
2017	1963	void nxt, nxt_chain;
2018		- uint32_t *last_chain = NULL;
	1964	+ __be32 *last_chain = NULL;
2019	1965	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2020	1966
2021		- flags = 0;
2022		- ha->fw_dump_cap_flags = 0;
	1967	+ lockdep_assert_held(&ha->hardware_lock);
2023	1968
2024		-#ifndef __CHECKER__
2025		- if (!hardware_locked)
2026		- spin_lock_irqsave(&ha->hardware_lock, flags);
2027		-#endif
	1969	+ ha->fw_dump_cap_flags = 0;
2028	1970
2029	1971	if (!ha->fw_dump) {
2030	1972	ql_log(ql_log_warn, vha, 0xd00c,
2031	1973	"No buffer available for dump!!!\n");
2032		- goto qla83xx_fw_dump_failed;
	1974	+ return;
2033	1975	}
2034	1976
2035	1977	if (ha->fw_dumped) {
2036	1978	ql_log(ql_log_warn, vha, 0xd00d,
2037	1979	"Firmware has been previously dumped (%p) -- ignoring "
2038	1980	"request...\n", ha->fw_dump);
2039		- goto qla83xx_fw_dump_failed;
	1981	+ return;
2040	1982	}
2041	1983	QLA_FW_STOPPED(ha);
2042	1984	fw = &ha->fw_dump->isp.isp83;
2043	1985	qla2xxx_prep_dump(ha, ha->fw_dump);
2044	1986
2045		- fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
	1987	+ fw->host_status = htonl(rd_reg_dword(&reg->host_status));
2046	1988
2047	1989	/*
2048	1990	* Pause RISC. No need to track timeout, as resetting the chip
..	..	@@ -2050,24 +1992,24 @@
2050	1992	*/
2051	1993	qla24xx_pause_risc(reg, ha);
2052	1994
2053		- WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
	1995	+ wrt_reg_dword(&reg->iobase_addr, 0x6000);
2054	1996	dmp_reg = &reg->iobase_window;
2055		- RD_REG_DWORD(dmp_reg);
2056		- WRT_REG_DWORD(dmp_reg, 0);
	1997	+ rd_reg_dword(dmp_reg);
	1998	+ wrt_reg_dword(dmp_reg, 0);
2057	1999
2058	2000	dmp_reg = &reg->unused_4_1[0];
2059		- RD_REG_DWORD(dmp_reg);
2060		- WRT_REG_DWORD(dmp_reg, 0);
	2001	+ rd_reg_dword(dmp_reg);
	2002	+ wrt_reg_dword(dmp_reg, 0);
2061	2003
2062		- WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
	2004	+ wrt_reg_dword(&reg->iobase_addr, 0x6010);
2063	2005	dmp_reg = &reg->unused_4_1[2];
2064		- RD_REG_DWORD(dmp_reg);
2065		- WRT_REG_DWORD(dmp_reg, 0);
	2006	+ rd_reg_dword(dmp_reg);
	2007	+ wrt_reg_dword(dmp_reg, 0);
2066	2008
2067	2009	/* select PCR and disable ecc checking and correction */
2068		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
2069		- RD_REG_DWORD(&reg->iobase_addr);
2070		- WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
	2010	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	2011	+ rd_reg_dword(&reg->iobase_addr);
	2012	+ wrt_reg_dword(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
2071	2013
2072	2014	/* Host/Risc registers. */
2073	2015	iter_reg = fw->host_risc_reg;
..	..	@@ -2076,73 +2018,73 @@
2076	2018	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
2077	2019
2078	2020	/* PCIe registers. */
2079		- WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
2080		- RD_REG_DWORD(&reg->iobase_addr);
2081		- WRT_REG_DWORD(&reg->iobase_window, 0x01);
	2021	+ wrt_reg_dword(&reg->iobase_addr, 0x7C00);
	2022	+ rd_reg_dword(&reg->iobase_addr);
	2023	+ wrt_reg_dword(&reg->iobase_window, 0x01);
2082	2024	dmp_reg = &reg->iobase_c4;
2083		- fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
	2025	+ fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
2084	2026	dmp_reg++;
2085		- fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
	2027	+ fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
2086	2028	dmp_reg++;
2087		- fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
2088		- fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
	2029	+ fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
	2030	+ fw->pcie_regs[3] = htonl(rd_reg_dword(&reg->iobase_window));
2089	2031
2090		- WRT_REG_DWORD(&reg->iobase_window, 0x00);
2091		- RD_REG_DWORD(&reg->iobase_window);
	2032	+ wrt_reg_dword(&reg->iobase_window, 0x00);
	2033	+ rd_reg_dword(&reg->iobase_window);
2092	2034
2093	2035	/* Host interface registers. */
2094	2036	dmp_reg = &reg->flash_addr;
2095		- for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
2096		- fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
	2037	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
	2038	+ fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
2097	2039
2098	2040	/* Disable interrupts. */
2099		- WRT_REG_DWORD(&reg->ictrl, 0);
2100		- RD_REG_DWORD(&reg->ictrl);
	2041	+ wrt_reg_dword(&reg->ictrl, 0);
	2042	+ rd_reg_dword(&reg->ictrl);
2101	2043
2102	2044	/* Shadow registers. */
2103		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
2104		- RD_REG_DWORD(&reg->iobase_addr);
2105		- WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
2106		- fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2045	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	2046	+ rd_reg_dword(&reg->iobase_addr);
	2047	+ wrt_reg_dword(&reg->iobase_select, 0xB0000000);
	2048	+ fw->shadow_reg[0] = htonl(rd_reg_dword(&reg->iobase_sdata));
2107	2049
2108		- WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
2109		- fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2050	+ wrt_reg_dword(&reg->iobase_select, 0xB0100000);
	2051	+ fw->shadow_reg[1] = htonl(rd_reg_dword(&reg->iobase_sdata));
2110	2052
2111		- WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
2112		- fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2053	+ wrt_reg_dword(&reg->iobase_select, 0xB0200000);
	2054	+ fw->shadow_reg[2] = htonl(rd_reg_dword(&reg->iobase_sdata));
2113	2055
2114		- WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
2115		- fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2056	+ wrt_reg_dword(&reg->iobase_select, 0xB0300000);
	2057	+ fw->shadow_reg[3] = htonl(rd_reg_dword(&reg->iobase_sdata));
2116	2058
2117		- WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
2118		- fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2059	+ wrt_reg_dword(&reg->iobase_select, 0xB0400000);
	2060	+ fw->shadow_reg[4] = htonl(rd_reg_dword(&reg->iobase_sdata));
2119	2061
2120		- WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
2121		- fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2062	+ wrt_reg_dword(&reg->iobase_select, 0xB0500000);
	2063	+ fw->shadow_reg[5] = htonl(rd_reg_dword(&reg->iobase_sdata));
2122	2064
2123		- WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
2124		- fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2065	+ wrt_reg_dword(&reg->iobase_select, 0xB0600000);
	2066	+ fw->shadow_reg[6] = htonl(rd_reg_dword(&reg->iobase_sdata));
2125	2067
2126		- WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
2127		- fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2068	+ wrt_reg_dword(&reg->iobase_select, 0xB0700000);
	2069	+ fw->shadow_reg[7] = htonl(rd_reg_dword(&reg->iobase_sdata));
2128	2070
2129		- WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
2130		- fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2071	+ wrt_reg_dword(&reg->iobase_select, 0xB0800000);
	2072	+ fw->shadow_reg[8] = htonl(rd_reg_dword(&reg->iobase_sdata));
2131	2073
2132		- WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
2133		- fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2074	+ wrt_reg_dword(&reg->iobase_select, 0xB0900000);
	2075	+ fw->shadow_reg[9] = htonl(rd_reg_dword(&reg->iobase_sdata));
2134	2076
2135		- WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
2136		- fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2077	+ wrt_reg_dword(&reg->iobase_select, 0xB0A00000);
	2078	+ fw->shadow_reg[10] = htonl(rd_reg_dword(&reg->iobase_sdata));
2137	2079
2138	2080	/* RISC I/O register. */
2139		- WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
2140		- fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
	2081	+ wrt_reg_dword(&reg->iobase_addr, 0x0010);
	2082	+ fw->risc_io_reg = htonl(rd_reg_dword(&reg->iobase_window));
2141	2083
2142	2084	/* Mailbox registers. */
2143	2085	mbx_reg = &reg->mailbox0;
2144		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
2145		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
	2086	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
	2087	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
2146	2088
2147	2089	/* Transfer sequence registers. */
2148	2090	iter_reg = fw->xseq_gp_reg;
..	..	@@ -2238,19 +2180,19 @@
2238	2180	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2239	2181	dmp_reg = &reg->iobase_q;
2240	2182	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
2241		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	2183	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
2242	2184
2243	2185	iter_reg = fw->resp0_dma_reg;
2244	2186	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2245	2187	dmp_reg = &reg->iobase_q;
2246	2188	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
2247		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	2189	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
2248	2190
2249	2191	iter_reg = fw->req1_dma_reg;
2250	2192	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2251	2193	dmp_reg = &reg->iobase_q;
2252	2194	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
2253		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	2195	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
2254	2196
2255	2197	/* Transmit DMA registers. */
2256	2198	iter_reg = fw->xmt0_dma_reg;
..	..	@@ -2456,16 +2398,16 @@
2456	2398
2457	2399	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2458	2400
2459		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2460		- RD_REG_DWORD(&reg->hccr);
	2401	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_RESET);
	2402	+ rd_reg_dword(&reg->hccr);
2461	2403
2462		- WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2463		- RD_REG_DWORD(&reg->hccr);
	2404	+ wrt_reg_dword(&reg->hccr, HCCRX_REL_RISC_PAUSE);
	2405	+ rd_reg_dword(&reg->hccr);
2464	2406
2465		- WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2466		- RD_REG_DWORD(&reg->hccr);
	2407	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_RESET);
	2408	+ rd_reg_dword(&reg->hccr);
2467	2409
2468		- for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
	2410	+ for (cnt = 30000; cnt && (rd_reg_word(&reg->mailbox0)); cnt--)
2469	2411	udelay(5);
2470	2412
2471	2413	if (!cnt) {
..	..	@@ -2506,19 +2448,28 @@
2506	2448
2507	2449	qla83xx_fw_dump_failed_0:
2508	2450	qla2xxx_dump_post_process(base_vha, rval);
2509		-
2510		-qla83xx_fw_dump_failed:
2511		-#ifndef __CHECKER__
2512		- if (!hardware_locked)
2513		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
2514		-#else
2515		- ;
2516		-#endif
2517	2451	}
2518	2452
2519	2453	/****************************************************************************/
2520	2454	/* Driver Debug Functions. */
2521	2455	/****************************************************************************/
	2456	+
	2457	+/* Write the debug message prefix into @pbuf. */
	2458	+static void ql_dbg_prefix(char *pbuf, int pbuf_size,
	2459	+ const scsi_qla_host_t *vha, uint msg_id)
	2460	+{
	2461	+ if (vha) {
	2462	+ const struct pci_dev *pdev = vha->hw->pdev;
	2463	+
	2464	+ /* <module-name> [<dev-name>]-<msg-id>:<host>: */
	2465	+ snprintf(pbuf, pbuf_size, "%s [%s]-%04x:%lu: ", QL_MSGHDR,
	2466	+ dev_name(&(pdev->dev)), msg_id, vha->host_no);
	2467	+ } else {
	2468	+ /* <module-name> [<dev-name>]-<msg-id>: : */
	2469	+ snprintf(pbuf, pbuf_size, "%s [%s]-%04x: : ", QL_MSGHDR,
	2470	+ "0000:00:00.0", msg_id);
	2471	+ }
	2472	+}
2522	2473
2523	2474	/*
2524	2475	* This function is for formatting and logging debug information.
..	..	@@ -2534,12 +2485,13 @@
2534	2485	* msg: The message to be displayed.
2535	2486	*/
2536	2487	void
2537		-ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
	2488	+ql_dbg(uint level, scsi_qla_host_t vha, uint id, const char fmt, ...)
2538	2489	{
2539	2490	va_list va;
2540	2491	struct va_format vaf;
	2492	+ char pbuf[64];
2541	2493
2542		- if (!ql_mask_match(level))
	2494	+ if (!ql_mask_match(level) && !trace_ql_dbg_log_enabled())
2543	2495	return;
2544	2496
2545	2497	va_start(va, fmt);
..	..	@@ -2547,16 +2499,12 @@
2547	2499	vaf.fmt = fmt;
2548	2500	vaf.va = &va;
2549	2501
2550		- if (vha != NULL) {
2551		- const struct pci_dev *pdev = vha->hw->pdev;
2552		- /* <module-name> <pci-name> <msg-id>:<host> Message */
2553		- pr_warn("%s [%s]-%04x:%ld: %pV",
2554		- QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2555		- vha->host_no, &vaf);
2556		- } else {
2557		- pr_warn("%s [%s]-%04x: : %pV",
2558		- QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2559		- }
	2502	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), vha, id);
	2503	+
	2504	+ if (!ql_mask_match(level))
	2505	+ trace_ql_dbg_log(pbuf, &vaf);
	2506	+ else
	2507	+ pr_warn("%s%pV", pbuf, &vaf);
2560	2508
2561	2509	va_end(va);
2562	2510
..	..	@@ -2577,11 +2525,11 @@
2577	2525	* msg: The message to be displayed.
2578	2526	*/
2579	2527	void
2580		-ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2581		- const char *fmt, ...)
	2528	+ql_dbg_pci(uint level, struct pci_dev pdev, uint id, const char fmt, ...)
2582	2529	{
2583	2530	va_list va;
2584	2531	struct va_format vaf;
	2532	+ char pbuf[128];
2585	2533
2586	2534	if (pdev == NULL)
2587	2535	return;
..	..	@@ -2593,9 +2541,8 @@
2593	2541	vaf.fmt = fmt;
2594	2542	vaf.va = &va;
2595	2543
2596		- /* <module-name> <dev-name>:<msg-id> Message */
2597		- pr_warn("%s [%s]-%04x: : %pV",
2598		- QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
	2544	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), NULL, id + ql_dbg_offset);
	2545	+ pr_warn("%s%pV", pbuf, &vaf);
2599	2546
2600	2547	va_end(va);
2601	2548	}
..	..	@@ -2614,7 +2561,7 @@
2614	2561	* msg: The message to be displayed.
2615	2562	*/
2616	2563	void
2617		-ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
	2564	+ql_log(uint level, scsi_qla_host_t vha, uint id, const char fmt, ...)
2618	2565	{
2619	2566	va_list va;
2620	2567	struct va_format vaf;
..	..	@@ -2623,16 +2570,7 @@
2623	2570	if (level > ql_errlev)
2624	2571	return;
2625	2572
2626		- if (vha != NULL) {
2627		- const struct pci_dev *pdev = vha->hw->pdev;
2628		- /* <module-name> <msg-id>:<host> Message */
2629		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2630		- QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2631		- } else {
2632		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2633		- QL_MSGHDR, "0000:00:00.0", id);
2634		- }
2635		- pbuf[sizeof(pbuf) - 1] = 0;
	2573	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), vha, id);
2636	2574
2637	2575	va_start(va, fmt);
2638	2576
..	..	@@ -2672,8 +2610,7 @@
2672	2610	* msg: The message to be displayed.
2673	2611	*/
2674	2612	void
2675		-ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2676		- const char *fmt, ...)
	2613	+ql_log_pci(uint level, struct pci_dev pdev, uint id, const char fmt, ...)
2677	2614	{
2678	2615	va_list va;
2679	2616	struct va_format vaf;
..	..	@@ -2684,10 +2621,7 @@
2684	2621	if (level > ql_errlev)
2685	2622	return;
2686	2623
2687		- /* <module-name> <dev-name>:<msg-id> Message */
2688		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2689		- QL_MSGHDR, dev_name(&(pdev->dev)), id);
2690		- pbuf[sizeof(pbuf) - 1] = 0;
	2624	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), NULL, id);
2691	2625
2692	2626	va_start(va, fmt);
2693	2627
..	..	@@ -2713,14 +2647,14 @@
2713	2647	}
2714	2648
2715	2649	void
2716		-ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
	2650	+ql_dump_regs(uint level, scsi_qla_host_t *vha, uint id)
2717	2651	{
2718	2652	int i;
2719	2653	struct qla_hw_data *ha = vha->hw;
2720	2654	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2721	2655	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2722	2656	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2723		- uint16_t __iomem *mbx_reg;
	2657	+ __le16 __iomem *mbx_reg;
2724	2658
2725	2659	if (!ql_mask_match(level))
2726	2660	return;
..	..	@@ -2735,13 +2669,12 @@
2735	2669	ql_dbg(level, vha, id, "Mailbox registers:\n");
2736	2670	for (i = 0; i < 6; i++, mbx_reg++)
2737	2671	ql_dbg(level, vha, id,
2738		- "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg));
	2672	+ "mbox[%d] %#04x\n", i, rd_reg_word(mbx_reg));
2739	2673	}
2740	2674
2741		-
2742	2675	void
2743		-ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2744		- uint8_t *buf, uint size)
	2676	+ql_dump_buffer(uint level, scsi_qla_host_t vha, uint id, const void buf,
	2677	+ uint size)
2745	2678	{
2746	2679	uint cnt;
2747	2680
..	..	@@ -2783,16 +2716,7 @@
2783	2716	if (level > ql_errlev)
2784	2717	return;
2785	2718
2786		- if (qpair != NULL) {
2787		- const struct pci_dev *pdev = qpair->pdev;
2788		- /* <module-name> <msg-id>:<host> Message */
2789		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: ",
2790		- QL_MSGHDR, dev_name(&(pdev->dev)), id);
2791		- } else {
2792		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2793		- QL_MSGHDR, "0000:00:00.0", id);
2794		- }
2795		- pbuf[sizeof(pbuf) - 1] = 0;
	2719	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), qpair ? qpair->vha : NULL, id);
2796	2720
2797	2721	va_start(va, fmt);
2798	2722
..	..	@@ -2836,6 +2760,7 @@
2836	2760	{
2837	2761	va_list va;
2838	2762	struct va_format vaf;
	2763	+ char pbuf[128];
2839	2764
2840	2765	if (!ql_mask_match(level))
2841	2766	return;
..	..	@@ -2845,16 +2770,9 @@
2845	2770	vaf.fmt = fmt;
2846	2771	vaf.va = &va;
2847	2772
2848		- if (qpair != NULL) {
2849		- const struct pci_dev *pdev = qpair->pdev;
2850		- /* <module-name> <pci-name> <msg-id>:<host> Message */
2851		- pr_warn("%s [%s]-%04x: %pV",
2852		- QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2853		- &vaf);
2854		- } else {
2855		- pr_warn("%s [%s]-%04x: : %pV",
2856		- QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2857		- }
	2773	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), qpair ? qpair->vha : NULL,
	2774	+ id + ql_dbg_offset);
	2775	+ pr_warn("%s%pV", pbuf, &vaf);
2858	2776
2859	2777	va_end(va);
2860	2778